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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8879

    Authors: 吳政勳;Cheng-Shing Wu
    Contributors: 電機工程研究所
    Keywords: 座標旋轉數位計算器;超大型積體電路;向量旋轉;Vector Rotation;VLSI;CORDIC
    Date: 2002-07-05
    Issue Date: 2009-09-22 11:36:57 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 向量旋轉(Vector Rotation)在許多數位信號處理(DSP)的應用中被廣泛地使用。在 這篇論文中,我們首先引入一個新的設計概念,稱之為角度量化(Angle Quantization)。當所需的旋轉角度是事先預知的情形下,角度量化的概念可用來當 作一個設計的指標。以此角度量化為基礎,我們建立了一個統一的低複雜度╱高速度旋 轉演算法的設計架構(Design Framework)。數個現有的向量旋轉演算法,例如傳統座 標旋轉數位計算器(CORDIC)演算法、角度重新編碼(Angle Recoding)演算法、修改 之座標旋轉數位計算器(MVR-CORDIC)演算法、以及延伸基礎角度集合(EEAS)演算法 等均可套入這個統一的設計架構;這些演算法亦組成了所謂的向量旋轉座標旋轉數位計 算器家族(Vector Rotational CORDIC Family)。此外,對於上述的演算法我們也提 出了其相對應的最佳化搜尋演算法(Optimization Searching Algorithm)、比例修正 (Scaling Operation)、訊號量化雜訊比增進法(SQNR Refinement)、系統化的設計 流程(Systematic Design Flow)以及超大型積體電路架構。所有的演算法均有設計範 例來加以說明,且輔以完整的電腦模擬來證明其正確性。以此新的設計架構為基礎,我 們不僅可以實現高速度╱低複雜度的向量旋轉超大型積體電路架構,同時無須犧牲在定 點實現(Fixed-point Implementation)時的準確度。 Vector rotation is the key operation employed extensively in many digital signal processing (DSP) applications. In this dissertation, we introduce a new design concept called Angle Quantization (AQ). It can be used as a design index for vector rotational operation, where the rotational angle is known in advance. Based on the AQ process, we establish a unified design framework for cost-effective low-latency rotational algorithms and architectures. Several existing works, such as conventional CORDIC, AR-CORDIC, MVR-CORDIC, and EEAS-based CORDIC algorithm, can be fitted into the design framework, forming a Vector Rotational CORDIC Family. In addition, for MVR-CORDIC and EEAS-based CORDIC algorithm, we address their corresponding optimization searching algorithms, scaling operations, SQNR refinement schemes, systematic design flow, and VLSI architectures. All the statements are supported by extensive computer simulations and design examples. Based on the new design framework, we can realize high-speed/low-complexity rotational VLSI circuits, whereas without degrading the precision performance in fixed-point implementations.
    Appears in Collections:[電機工程研究所] 博碩士論文

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