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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8928

    Title: 應用於通訊系統的內嵌式數位訊號處理器架構;Embedded DSP Core Architecture for Communication Applications
    Authors: 劉金茂;Jin-Mao Liu
    Contributors: 電機工程研究所
    Keywords: 數位訊號處理器;DSP Processor
    Date: 2000-07-14
    Issue Date: 2009-09-22 11:37:49 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 今天, 數位訊號處理器(DSP Procesor)是許多通信系統和嵌入的系統的心臟。本論文主要是研究發展一種低價位,可以重複使用,開發時間短,並且可以根據顧客的規格產生數位訊號處理器處理機的架構。 在本論文中,我們根據近幾年所提出有關數位訊號處理器的架構及參數化訊號處理器的設計方法等相關期刊論文,設計出符合我們所要的數位訊號處理器的架構,並且根據我們的需求提出此處理器的定址模式與指令集,並且解決了管線化架構(Pipeline Architecture) 所遭遇的問題。 最後,整顆晶片用Verilog語言描述完成,並且經過Synopsys公司所提供 的數位電路合成工具完成整顆晶片的模擬,本晶片總共使用27915.418 gate counts,並且工作於100MHz的速度。 Today, DSP processors are at the heart of many communication systems and embedded systems. The object of this thesis is to develop a DSP processor architecture that is suitable to be parameterized by user specification to obtain a DSP processor that has the characteristics of low cost, reusable, and short time-to-market. In this thesis, we survey several DSP processor architectures and the scheme of parameterized DSP processor core in recent years. Then, we propose a DSP processor architecture that can be parameterized. In addition, we also address the addressing modes in the DSP processor according to the characteristic of DSP algorithm. For high performance DSP processor, we also modify the architecture of MAC unit and design suitable pipeline stages in the processor. We also propose the solutions of pipeline hazard to resolve the pipeline stall. Finally, the DSP processor is described with Verilog hardware description language and synthesized by Synopsys. From the synthesis reports, the total gate counts are 27915.418 gates and can operate in 100MHz.
    Appears in Collections:[電機工程研究所] 博碩士論文

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