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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8940

    Title: 適用於通訊系統之李德所羅門軟性智慧財產模組自動產生器;Soft IP Generator of Reed-Solomon Codec for Communication Systems
    Authors: 施志隆;Chih-Lung Shih
    Contributors: 電機工程研究所
    Keywords: 單晶片系統;智慧財產;軟性智慧財產;李德所羅門碼;SOC;IP;Soft IP;Reed-Solomon code
    Date: 2000-06-26
    Issue Date: 2009-09-22 11:38:02 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 由於現今超大型積體電路(VLSI)的快速發展,使得"單晶片系統" (SOC)逐漸成為主流。這種新的積體電路設計方式的複雜度比傳統的設計高出許多,所以使用快速雛型產生器及智慧財產(IP)設計模組的再利用可以減少設計人員的負擔及提高設計效率。 在本論文中,我們選擇李德所羅門碼(Reed-Solomon code)為研究主題,設計一個RS code 的快速雛型產生器。在通訊系統中,我們可以發現RS code經常被應用在更正通道所引起的錯誤。對於叢集錯誤(Bursty error)與隨機錯誤(Random error),RS code可以提供很好的錯誤更正能力,因此成為非常受歡迎的通道編碼方式之一;也因為這個重要的因素,使得RS code被應用在許多的傳輸系統上,例如無線通訊系統、纜線數據機(Cable modem)、電腦記憶體、非對稱性數位用戶迴路(ADSL)等。 我們首先完整地完成一次RS code的ASIC設計流程,以瞭解設計技術。我們依據此經驗成為以暫存器轉換階層(RTL)來實現RS code的設計方法。然後,我們將上述結果納入快速雛型產生器的設計流程。我們的快速雛型產生器可接受系統規格,如RS code 系統的 n,k,m值,再根據設計流程方法產生可合成的高階硬體描述語言-Verilog,以供特定應用積體電路(ASIC)或現場可程式邏輯閘陣列(FPGA)使用。此外,為了更適合不同系統中的應用,我們特別加入了一些參數,如編碼器架構的選擇與解碼器的演算法等,我們並針對不同的架構做比較,分析面積、速度與功率。最後,我們提供了一個利用快速雛型產生器來產生ADSL之RS codec的例子。 Recent rapid progress in VLSI technology has led to an emerging theme - "System-on-a-chip." The complexity of new design paradigm is much higher than conventional IC designs; Hence, it calls for rapid prototyping and design reuse of major IP modules so as to alleviate the designer's effort and to speed up the design process. In this thesis, we focus on the topic of Reed-Solomon codes. We develop a rapid prototyping system for RS encoder, and decoder. In the communication systems, RS codes have a widespread use to provide error protection. For bursty errors and random errors, RS code has become a popular choice to provide data integrity due to its good error correction capability. This feature has been one of the important factors in adopting RS codes in many practical applications such as wireless communication system, cable modem, computer memory and ADSL systems. We first go through the complete ASIC design flow to explore the design techniques in RS codec. The design experience will be formulated to form the complete design methodology of the FEC modules at the register-transfer level (RTL). Then we incorporate the knowledge into our RS code generator design flow. Our RS code generator can be given the specification of FEC system ( e.g., n, k ). We follow a design methodology to automatically generate the synthesizable Verilog (hardware description language) codes. With the generated Verilog codes, we can apply high-level synthesis tool such as Synopsys Design Analyzer and FPGA Express to generate the netlist for ASIC or FPGA implementations. In addition, we explore the design parameters for different systems such as architectures of RS encoder and algorithms of RS decoder. We also analyze the results of area, timing, and power with different choices. Finally, we generate the RS codec of ADSL with our RS code generator as an example.
    Appears in Collections:[電機工程研究所] 博碩士論文

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