在本篇論文中，我們提出了一種新的時序與資料回復的方法。相較於傳統所用的鎖相迴路，我們採用了現今相當流行的相位選擇架構。在此設計中，我們利用對資料的五倍過取樣程序，從所獲得的訊息中萃取出資料轉變狀態的位置。由此，我們便可以知道最佳的資料取樣位置。 資料轉態的位置會受到靜態相位錯誤或相位抖動的影響而漂移，這樣的非理想現象將造成系統訊雜比與時序邊限的降低。因此，我們必須設法去追蹤這樣的漂移並且做資料回復。 在我們的設計中，利用了多數閘來增加資料的可信賴度，並且由互斥閘來得到資料轉態的情形。接下來我們使用信賴計數器來統計資料轉態的結果，並且決定最佳取樣點的位置。 除此之外，我們建立了一套資料錯誤率的預測與分析方法。由這個分析的結果，設計者可以根據所需要的規格來選擇適當的系統參數並避免做過多的錯誤嘗試。 最後，我們使用了可程式閘陣列來做硬體的功能驗證，並且內建了一個錯誤計數模組來計算資料錯誤的比率。 In this thesis, a novel timing and data recovery algorithm for high-speed serial link is proposed. Instead of using the traditional PLL, we use the phase picking architecture. In our design, a 5X oversampling using multi-phase clocks are used to obtain the data information. And our purpose is to find the data transition position and pick the optimum phase for data sampling according to such information. The transition point may move due to static phase error or jitters (dynamic phase error due to noise). These non-ideal effects cause the reduction of SNR and timing margin. So, the system should detect the phase errors and output a recovery clock to track it. First, a majority voter chain is applied to enhance the data reliability. Then the transition position of each bit can be detected by XOR. The transition information are accumulated in the confidence counter and the machine will decide that whether the sampling phase should change. By such recovery mechanism, the sampling phase is fixed at the central point of data. Finally, according to the phase selected, three sample values are processed by a majority voter to obtain the recovered data. Besides, we also develop an analysis method for bit error rate prediction according to the different system parameters. By the analysis results, one can decide the system parameters depend on the design specifications instead of iterations. Finally, we use Xilinx FPGA for function simulation of the recovery system. Moreover, a bit error measurement modules are built in to test the system performance.
