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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8960


    Title: 第二代高速數位用戶迴路中維特比解碼器之FPGA實現;FPGA Realization of the Viterbi Decoder for HDSL2 Systems
    Authors: 羅鋒;Feng Lo
    Contributors: 電機工程研究所
    Keywords: 第二代高速數位用戶迴路;迴旋碼;維等比解碼器;維等比演算法;HDSL2;concolutional code;Viterbi Decoder;Viterbi Algorithm
    Date: 2000-07-17
    Issue Date: 2009-09-22 11:38:24 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 第二代高速數位用戶迴路(HDSL2)被認為是使T1(1.544Mbps)服務更有經濟效率的解決方案。其最大的特點在於利用目前已架構的電話線用戶迴路即可提供T1服務,而且傳輸距離比既有的解決方案還遠。為達此目標,在HDSL2標準中,使用由脈衝振幅調變(PAM)及迴旋碼(convolutional code)所組成格子碼(TCM)為編碼標準。 在本論文中,我們實現了適用於HDSL2系統之迴旋碼編/解碼器。相較於編碼器,解碼器的電路複雜了許多,而且在實際硬體實現時,有許多要素需要列入考慮。在設計的過程中,我們針對實現維特比解碼器(Viterbi decoder)的要素加以探討,並且選定我們所要採用的架構;接著,我們以Matlab程式驗證整個編/解碼運作的過程,並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後,我們以Altera FLEX 10K200E來實現我們的設計。 High bit rate Digital Subscriber Line-2nd Generation (HDSL2) has been considered to make T1 more cost-efficient. HDSL2 delivers full-duplex T1 payload over one copper pair, and it offers a reach of 12,000 feet per span that is much over traditional T1 delivery. The Trellis-Coded Modulation (TCM) that consists of Pulse Amplitude Modulation (PAM) and the convolutional code is adopted as the line code scheme. In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device.
    Appears in Collections:[電機工程研究所] 博碩士論文

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