無接面鐵電場效電晶體與量測模式對增強極化之影響;Polarization Enhancement of Junctionless Ferroelectric FETs considering the Effects of Measurement Schemes

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題名:	無接面鐵電場效電晶體與量測模式對增強極化之影響;Polarization Enhancement of Junctionless Ferroelectric FETs considering the Effects of Measurement Schemes
作者:	傅文岑;Fu, Wen-Tsen
貢獻者:	電機工程學系
關鍵詞:	鐵電電晶體記憶體;極薄通道;無接面;耐久度;記憶窗戶;量測;Ferroelectric;Memory Window;Junctionless;Measurement;Wake Up Free
日期:	2022-08-04
上傳時間:	2022-10-04 12:05:44 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文討論鐵電材料-氧化鉿鋯(Hf1-xZrxO2，HZO)極薄通道無接面鐵電場效電晶體(Ultra Thin Channel Junctionless Ferroelectric FET )加入不同量測電壓時的鐵電現象，其中針對鐵電元件擁有的非理想效應喚醒效應(Wake Up Effect)進行探討，而喚醒效應指的是鐵電元件在操作前都要加入多個喚醒電壓，才能使鐵電元件擁有完整的鐵電效應，而施加多個喚醒電壓會造成耐久度(Endurance)的下降，也因此本篇論文提出在不影響耐久度的狀況下可以完全喚醒的量測手法。本論文於實驗中製作極薄通道無接面鐵電場效電晶體，其結構是由水平爐管(Horizontal Furnace)低真空化學氣相沉積(Low-Pressure Chemical Vapor Deposition, LPCVD)出50nm n+-poly-Silicon 當作源極/汲極(Source/Drain)，接著在源極/汲極上沉積厚度8nm-n+-poly-Silicon作為極薄通道，而閘極層(Gate Stack)分別是由原子層沉積(Atomic Layer Deposition, ALD)厚度為10nm的HZO作為鐵電層(Ferroelectric Layer)，頂層金屬(Top Metal)則是由物理氣相沉積(Physical Vapor Deposition, PVD) TiN 80nm，然後快速熱退火700°C 30sec去達到鐵電的結晶化(Crystallization)，完成閘極堆疊後沉積出二氧化矽保護層(Passivation Oxide)，透過金屬化(Metalization)完成最後與金屬導線的連接並結束製程。本論文探討不同喚醒電壓對鐵電元件鐵電性之影響，量測過程中先加入三種不同的實驗電壓包含FWFS(Forward Wake up Forward Sensing)、FWRS(Forward Wake up Reverse Sensing)、RWFS(Reverse Wake up Forward Sensing)，量測結果發現已經喚醒過的鐵電元件可以透過相對電壓差(Relative Voltage)去增加更多有效轉換偶極子(Effective Switching Dipoles)，進而增加鐵電元件在操作下擁有更好的鐵電能力其中包含更大的記憶窗戶(Memory Window)和優化次臨界擺幅(Subthreshold Swing)。實驗結果顯示在喚醒後透過相對電壓差所增加的有效轉換偶極子不會受到後續操作過程而改變，也因此透過這一特性設計出無喚醒電壓的操作(Nearly Wake Up Free)的實驗，用簡單的電壓順序造成相對電壓差來取代傳統喚醒電壓，使得鐵電元件可以在比傳統喚醒電壓的元件還要更早的喚醒，即縮短其所需之喚醒電壓操作次數，並擁有更高的記憶視窗(Memory Window)，其耐久度量測可以與傳統使用喚醒電壓的元件一樣承受超過100萬次的雙極性電壓波形操作。 ;In this thesis, to optimize the non-ideal wake-up effect, we analyzed the impact of different measurement voltages on ultra-thin channel Junctionless Ferroelectric FET (FeFET). The non-ideal wake-up effect exists in the Ferroelectric FET operations. To activate the dipoles in the Ferroelectric (FE) layer, we usually use multiple bipolar voltages, which causes damage to the ferroelectric and insulating layers and forces the endurance to degrade. The ultra-thin channel junctionless Ferroelectric FET was fabricated to analyze the wake-up effect. We used Horizontal Furnace to deposit 50 nm n+poly-Si Source/Drain and 8 nm n+poly-Si ultra-thin channel. The gate stack was fabricated sequentially by ALD HZO 10 nm, PVD TiN 80 nm, and then RTP 700°C for 30 sec to achieve ferroelectric (FE) phase crystallization. After that, metallization was performed to complete the device fabrication. Three different voltage schemes, including Forward Wake up Forward Sensing (FWFS), Forward Wake up Reverse Sensing (FWRS), and Reverse Wake up Forward Sensing (RWFS) for junctionless FeFETs, are considered to analyze the impact of the wake-up effect. We found that ferroelectric devices can obtain more effective switching dipoles than traditional wake-up voltage schemes by the relative voltages between the end of wake-up and the start of sensing voltages. Extra effective switching dipoles caused by the relative voltage can improve ferroelectricity and memory window. Relative voltage can induce switching dipoles. We design a nearly wake-up-free experiment, using a large relative voltage to replace traditional wake-up voltages, which increases switching dipoles. Compared with conventional wake-up voltage, the nearly wake-up free voltage can induce the switching dipoles without adding bipolar voltages and optimize ferroelectric devices at the beginning of the measurement experiment—the improvement of ferroelectricity, including memory window and subthreshold swing.
顯示於類別:	[電機工程研究所] 博碩士論文

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