| 摘要: | 相位陣列系統用於收發機前端，用於調整波束方向以達到波束成
形；不論是雷達系統或是第五代行動通訊，相位陣列均有不可替代之
地位。相位陣列通常由相位偏移器與可變增益放大器再根據發射或接
收端搭配功率放大器或低雜訊放大器所組成，達成一可調相位與振幅
之目標，因此不論是相位偏移器或是可變增益放大器都是相位陣列中
關鍵電路元件。本論文中，分別提出一數位式相位偏移器與數位式可
變增益放大器操作於 K 頻段，並且使用 TSMC 0.18-µm CMOS 製程
實現之。
第二章中，我們使用 TSMC 0.18-µm CMOS 製程實現一 K 頻段
五位元被動式相位偏移器，11.25◦、22.5◦、45◦、90◦相位偏移器為使
用傳輸線基準全通網路之全通式網路架構，180◦相位偏移器則使用
SPDT 架構實現。此晶片共分為兩個版本，由第一個版本量測結果中
我們發現 TSMC 0.18-µm CMOS 製程中 MIM 電容的 model 可能有多
估之寄生電感，因此我們於重新模擬中將 MIM 電容旁串聯負電感，
藉此扣掉多估的寄生效應。最後於第二個版本重新設計微調電容以修
正各式參數，重新設計結果顯示均方根相位誤差於 20.4 GHz 至 31.1
GHz 均低於 4◦；返回損耗於頻寬內皆低於 11.2 dB；植入損耗於頻寬
小於 17.1 dB；均方根振幅誤差小於 0.5 dB。
第三章中，我們使用 TSMC 0.18-µm CMOS 製程實現一 K 頻段
五位元可變增益放大器，以數位式切換偏壓達到不同狀態之增益，
電路由五路全差動疊接放大器架構並聯組成，輸入端使用 1:2 變壓
器匹配、輸出端則使用先串聯電容在並聯電感的 L 型匹配網路。本
電路主要應用於 ISM 頻段（24 -24.5 GHz），模擬結果顯示於全開狀
態（s = 31）下輸入返回損耗皆大於 18.62 dB、輸出返回損耗皆大於
11.53 dB、增益皆大於 10.56 dB、相位變化為 37◦。量測結果顯示增
益峰值由 24 GHz 頻偏至 21.9 GHz，全開狀態下輸入返回損耗為 13.5
dB；輸出返回損耗為 5 dB；增益為 5.7 dB；相位變化為 25.7◦，整體
來說除了相位變化有降低外，其他數據量測均比模擬差，特別是增益
與輸出返回損耗。重新模擬時我們將忽略之走線帶入，包含輸入端、
輸出端與電晶體間之走線，帶入後的確修正往低頻偏之趨勢。為了使
返回損耗與增益貼合量測結果，我們於輸入端變壓器旁並聯電阻及輸
出端電感旁串聯電阻。重新模擬結果後增益峰值頻率為 21.8 GHz ，
於增益峰值頻率全開的狀態下，輸入返回損耗為 13 dB、輸出返回損
耗為 5 dB、增益為 5.7 dB、相位變化最大為 30◦，由此可知藉由重新
模擬除了相位變化還是與量測相比大約 4◦外，其他數據均貼合量測結
果。另外以本架構來說，於相位變化對頻率作圖發現，於增益峰值附
近都有較大之相位變化，值得後續討論與改善。
本論文中，我們實現了 K 頻段數位式相位偏移器與可變增益放
大器，以結論來說相位偏移器經過重新設計後以非常接近模擬，而可
變增益器經過重新模擬後也能貼合量測，利用以上經驗我們可以推估
TSMC 0.18-µm CMOS 製程於 K 頻段有哪些需要注意那些寄生效應，
使我們往後的電路模擬可以更加精準。;The phased array system is used in the front end of the transceiver to adjust the beam direction to achieve beamforming, whether it is a radar system or a fifth-generation mobile communication, the phased array has an irreplaceable position. The phase array is usually composed of a phase shifter and a variable gain amplifier, and then is matched with a power amplifier or a low noise amplifier according to the transmitting or receiving end to achieve an adjustable phase and amplitude. Variable gain amplifiers are key circuit elements in phased arrays. In this paper, a digital phase shifter and a digital variable gain amplifier are respectively proposed to operate in the K band, and implemented using TSMC 0.18-µm CMOS process.
In Chapter 2, we use TSMC 0.18-µm CMOS process to implement a K band five-bit passive phase shifter, 11.25◦, 22.5◦, 45◦, 90◦ phase shifter is an all-pass network architecture using the transmission line reference all-pass network, and the 180◦ phase shifter is implemented using the SPDT architecture. This chip is divided into two versions. From the measurement results of the first version, we found that the model of the MIM capacitor in the TSMC 0.18-µm CMOS process may overestimate the parasitic inductance, so we connected the MIM capacitor in series in the re-simulation. Negative inductance, thereby deducting the parasitic effect of overestimation. Finally, in the second version, the trimmer capacitors were redesigned to correct various parameters. The redesign results showed that the RMS phase error was lower than 4◦ from 20.4 GHz to 31.1 GHz, the return loss was lower than 11.2 dB, insertion loss is less than 17.1 dB in bandwidth, RMS amplitude error is less than 0.5 dB.
In Chapter 3, we use TSMC 0.18-µm CMOS process to implement a K frequency band five-bit variable gain amplifier, and digitally switch the bias voltage to achieve the gain of different states. The circuit consists of five fully differential stacks. The amplifier structure is composed of parallel connection, the input end uses a 1:2 transformer matching, and the output end uses an L-type matching network with a series capacitor and a parallel inductor. This circuit is mainly used in the ISM frequency band (24-24.5 GHz). The simulation results show that the input return loss is greater than 18.62 dB, the output return loss is greater than 11.53 dB, and the gain is greater than 10.56 dB, and the phase change is 37◦. The measurement results show that the peak gain is shifted from 24 GHz to 21.9 GHz, and the input return loss is 13.5 dB in the fully open state, the output return loss is 5 dB, the gain is 5.7 dB, the phase change is 25.7◦, overall Except for the reduction in phase variation, all other data measurements are worse than the simulation, especially the gain and output return loss. When re-simulating, we will bring in the neglected traces, including the traces between the input terminal, the output terminal and the transistor. After bringing in the traces, we will indeed correct the trend of low frequency deviation. In order to make the return loss and gain fit the measurement results, we put a resistor in parallel next to the transformer at the input and a series resistor next to the inductor at the output. After re-simulating the results, the gain peak frequency is 21.8 GHz. When the gain peak frequency is fully open, the input return loss is 13 dB, the output return loss is 5 dB, the gain is 5.7 dB, and the maximum phase change is 30◦. It can be seen that by re-simulating, except for the phase change, which is about 4◦ compared with the measurement, other data are consistent with the measurement results. In addition, according to the present architecture, the phase change is plotted against the frequency, and it is found that there is a large phase change near the gain peak, which is worthy of subsequent discussion and improvement.
In this paper, we implemented a K band digital phase shifter and variable gain amplifier, and concluded that the phase shifter was redesigned to be very close to analog, and the variable gain was re-simulated It can also be fitted and measured later. Using the above experience, we can estimate the parasitic effects of the TSMC 0.18-µm CMOS process in the K band, so that our future circuit simulation can be more accurate. |
