| 摘要: | 隨著半導體製程技術的進步，作為現今資料傳輸的主要架構，高速串列連結系統(High-Speed Serial Link System)正被推向更高的資料速率以滿足頻寬需求的爆炸性增長。在增加傳輸頻寬與功能的同時，高速串列連結系統必須與當前規格兼容，以滿足特定平台的需求。此外，為了減少重複設計，高速串列連結系統必須設計為適應各種操作條件以滿足不同的應用。因此，自適應設計在現今的高速串列連結系統中起著重要作用。
隨著資料傳輸速率被推到更高，收發器(Transceiver)還必須與當前標準兼容，以滿足各別平台的頻寬需求。然而，前向時脈架構(Forwarded Clock Architecture)中的接收器(Receiver, RX)的可用範圍受到延遲鎖定迴路(Delay-Locked Loop, DLL)的操作範圍所限制。因此，本文提出一個適用於各種雙倍資料速率(Double Data Rate, DDR)記憶體應用的寬範圍全數位延遲鎖定迴路。為了延伸操作範圍，所提出之架構透過諧波鎖定偵測與自動校正技術來改變目標鎖定週期，從而解決諧波鎖定問題。實驗結果表明所提出之延遲鎖定迴路的操作範圍為0.1至2.7 GHz，其中最大鎖定時間為143個週期。
此外，隨著資料速率的不斷提高，傳輸介質的頻寬限制嚴重衰減了傳輸資料的高頻成分。此衰減增加了資料的轉態時間，從而影響相鄰資料的轉態位置與擺幅，稱為符碼間干擾(Intersymbol Interference, ISI)。現今收發器通常採用多種等化器補償符碼間干擾，使得補償過程複雜化。除此之外，不同的傳輸介質與纜線長度所對應的損耗曲線彼此之間也存在顯著差異。這些因素導致等化器無法最佳化補償並降低接收資料的訊號完整度(Signal Integrity, SI)。因此，本文提出一個統一的自適應系統，可以應用於不同的等化器並實現準確的自適應。所提出的自適應系統提取目標符碼間干擾，並相應地獨立調整每個等化器的補償增益。實驗結果表明，所提出的自適應等化器的補償範圍為2.6至22.6 dB，補償範圍比為8.69。在5 Gb/s時的總功率消耗為12.5 mW。
除了符碼間干擾之外，高資料速率還會導致傳輸資料受到電源與設備雜訊，以及發射器與接收器之間頻率不匹配的影響。這些干擾導致傳輸資料抖動並降低收發器的誤碼率(Bit Error Rate, BER)。為了確保功能正確，時脈與資料回復電路(Clock and Data Recovery Circuit, CDR)必須容忍抖動，並恢復資料與時脈。因此，本文採用數位自適應迴路增益控制器與低擺幅的數位類比轉換器(Digital-to-Analog Converter, DAC)來提高時脈與資料回復電路的抖動容忍度(Jitter Tolerance, JTOL)效能。自適應迴路增益控制器根據輸入抖動來動態調整時脈與資料回復電路的迴路增益，從而提升相位追蹤能力。而低擺幅的數位類比轉換器降低了輸出非線性與脈衝干擾，從而降低了迴路增益不匹配與相位偏移。這些設計技術改善了時脈與資料回復電路的相位追蹤行為，進而提高了抖動容忍度效能。此外，由於所提出之自適應迴路增益控制器採用簡易的數位邏輯電路實現，因此具有低功耗、小面積與可靠的特色。實驗結果表明，抖動容忍度在控制範圍內均得到改善，且最小抖動容忍度為0.4 UIpp。操作在5 Gb/s時的時脈與資料回復電路整體功耗為16.8 mW。
這些本文所提出的技術可以有效提升串列連接接收器的工作範圍、可補償通道衰減範圍以及抖動容忍度，進而強化接收器的可適性以滿足應用需求。;Owing to the advancements in semiconductor fabrication technology, as the major architecture in modern data transmission, high-speed serial link systems are being pushed to higher data rates to meet the explosion of bandwidth requirements. While increasing transmission bandwidth and functionality, the high-speed serial link systems must be compatible with current standards to satisfy platform-specific requirements. Additionally, in order to reduce repetitive design, high-speed serial link systems must be designed to be accommodate a variety of operating conditions to meet different applications. Thus, the concept of adaptive design plays an important role in modern high-speed serial link systems.
As the transmitted data rates have been pushed to higher, the transceivers must also be compatible with current standards to satisfy platform-specific bandwidths. However, the operating range of receivers (RXs) in the forwarded clock architecture is limited by the operating range of delay-locked loops (DLLs). Thus, this dissertation proposes a wide-range all-digital DLL for various double data rate (DDR) memory applications. To extend the operating range, the proposed architecture adopts the harmonic locking detection and autocalibration technologies to change the target locking cycle, thereby solving the harmonic locking problem. The experimental results indicate that the operating range of the proposed DLL was from 0.1 to 2.7 GHz with a maximum locking time of 143 cycles.
Besides, as the data rates continue to increase, the bandwidth limit of transmission medium severely attenuates the high-frequency content of the transmitted data. This attenuation increases the transition time of data, thereby affecting the transition position and swing of adjacent data, which is called intersymbol interference (ISI). Modern transceivers usually employ various equalizers to compensate the ISI, which complicates the compensation process. In addition, the corresponding loss profile is significant different from each other because of variations in transmission medium and cable length. These factors result in suboptimal equalization and degrade the signal integrity (SI) of the received data. Therefore, this dissertation proposes a unified adaptation system that can be applied to different equalizers and achieve accurate adaptation. The proposed adaptation system extracts target ISI and independently adjusts the compensation gain of each equalizer accordingly. The experimental results indicate the compensation range of proposed adaptive equalizer was 2.6–22.6 dB, and the compensation range ratio was 8.69. The total power consumption at 5 Gb/s was 12.5 mW.
In addition to the ISI, the high data rates result in the transmitted data suffer from power and device noises, as well as frequency mismatches between transmitters and receivers. These disturbances affect data jitter and degrades the bit error rate (BER) of transceivers. To ensure functionality, clock and data recovery circuits (CDRs) must tolerate jitters, and recover data and clock. Thus, this dissertation adopts a digital adaptive loop gain controller (ALGC) and a low-swing digital-to-analog converter (DAC) to improve the jitter tolerance (JTOL) performance of CDR. The ALGC dynamically adjusts the loop gain of CDR according to the input jitter, thereby improving the phase tracking capability. The low-swing DAC decreases the output nonlinearity and glitches, thereby decreasing the loop gain mismatch and phase offset. These design techniques improve the phase tracking behavior of CDR, therefore enhancing JTOL performance. Additionally, since the proposed ALGC is implemented by a simple digital logic circuit, it has the characteristics of low power consumption, small area, and reliability. The experimental results demonstrated that the JTOL performance was improved within the control range, with a minimum JTOL of 0.4 UIpp. The total power consumption of CDR when operating at 5 Gb/s was 16.8 mW.
These technologies proposed in this dissertation can effectively improve serial link RX in terms of operating range, compensable channel loss range, and JTOL, thereby enhancing the adaptability of RX to meet the requirements of applications. |
