高速以太網傳輸系統中，如5GBASE-T系統，迴音干擾和近端干擾(NEXT)是兩個主要議題。本論文依據 IEEE 802.3bz™-2016 規範標準 [1]，設計出乙太網路傳輸之數位基頻收發機晶片來送收PAM-16編碼之訊號。傳統方法使用自適應有限脈衝(Finite Impulse Response, FIR)濾波器複製迴音路徑之通道效應，使通過迴音路徑與通過迴音消除器之訊號相同，進而扣除迴音。惟使用傳統方法將因有限脈衝濾波器長度過長而花費大量硬體成本，因此如何在符合規範效能下有效地降低硬體成本將是首要課題。本論文所採用之迴音通道模型，在尾段(Tail)部分有因近端(Near end)與遠端(Far end)傳輸不匹配造成之小幅度反射波(Reflection)，且反射波位置將因通道長度不同而有所改變，因此現存文獻提出之方法無法達到期望之效能，抑或是電路成本居高不下。本論文使用有限脈衝響應(FIR)、無限脈衝響應(Infinite Impulse Response, IIR)濾波器進行模擬分析，藉由穩定性準則克服無限脈衝響應濾波器可能造成系統無法收斂之情形，而近年來人工智慧相關技術蓬勃發展，本論文亦結合機器學習與自適應濾波器，在既符合規範標準下，降低迴音消除器電路之成本。 硬體實現之部分使用Verilog HDL描述與模擬，透過SMIMS VeriEnterprise Xilinx FPGA與晶片設計工具Design Compiler與IC Compiler在TSMC-40nm製程下驗證其電路功能。 ;In many high speed Ethernet transmission systems, such as 5 GBASE-T system, echo and near-end crosstalk (NEXT) interferences are two major impairments. This work designs the digital baseband transceiver for Ethernet transmission using PAM-16 signal based on standard IEEE 802.3bz™-2016. Conventional echo cancellation is performed using noise cancellers which are usually implemented using adaptive finite impulse response (FIR) filters, where the replica of echo interferences estimated by FIR filters are subtracted from the received noisy signals. This traditional approach, however, requires a significant hardware cost as the number of taps in the adaptive FIR filters is large. Therefore, it is important to reduce hardware cost. The issue of how to decrease the cost of the circuit while meeting the performance requirements has been paid more and more attention. The echo channel model used in this paper has a small reflection in the tail part due to the mismatch between the transmission of the near end and the far end echo. Position of the reflection will be determined by the cable length, so the methods proposed in the traditional literature cannot achieve the desired performance, or the circuit cost remains high. In this paper, finite impulse response and infinite impulse response filters are used for simulation analysis, and the stability criterion is used to avoid the unstable situation. In recent years, artificial intelligence related technologies are developing vigorously. This paper also combines machine learning and adaptive filters to decrease the cost of echo canceller circuits. Regarding the hardware implementation, the Verilog HDL description is employed and the related simulations, are conducted. The circuit function is verified under the TSMC-40nm process through SMIMS VeriEnterprise Xilinx FPGA and chip design tools Design Compiler and IC Compiler.
