具接收端前饋式等化器補償之 10 Gb/s全速率接收端電路;A 10 Gb/s Full-Rate Receiver with RX-FFE Compensation

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題名:	具接收端前饋式等化器補償之 10 Gb/s全速率接收端電路;A 10 Gb/s Full-Rate Receiver with RX-FFE Compensation
作者:	王遠;Wang, Yuan
貢獻者:	電機工程學系
關鍵詞:	接收端前饋式等化器
日期:	2023-01-04
上傳時間:	2023-05-09 18:10:46 (UTC+8)
出版者:	國立中央大學
摘要:	隨著科技的進步，資料傳輸速率不斷提升，高速串列傳輸技術漸漸取代掉傳統並列傳輸方式，例如 HDMI、 Displayport、 USB、 SATA、 PCI-Express等。但因通道頻寬並未隨之上升，造成資料經過傳輸通道的衰減越為嚴重，因此將等化器應用於接收端，以補償資料來使訊號完整度上升被廣泛應用於近年來的發展。本論文提出一接收端前饋式等化器架構，其利用類比延遲電路將輸入訊號做出不同時間的延遲，並針對相對應之第一級前游標資料符碼間干擾乘上權重係數來進行消除。與傳統架構相比，其不需使用到時脈進行取樣和緩衝器電路，因此在維持資料振幅的同時，也可降低功率消耗。本論文在等化器架構上整合連續時間線性等化器、前饋式等化器及一階離散時間決策回授等化器來進行補償消除符碼間干擾，以達到降低硬體複雜度與整體功率消耗的效果來補償資料。本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程實現，電路操作電壓為 0.9 V輸入資料採用 10 Gb/s之 NRZ資料訊號，輸入時脈採用全速率 10 GHz時脈訊號，等化器可補償之通道衰減範圍為 7 dB至 33 dB，於佈局後模擬在通道衰減 7 dB時，補償後之眼圖眼高改善 22 佈局後模擬在通道衰減 33 dB時，補償後之眼圖眼高改善 47 %。整體功率消耗為 18.88 mW。 45nm/40nm微縮後之晶片面積為 1.060 mm2，其中核心電路面積為 0.026 mm2。;With the advancement of technology, the data transmission rate has been continuously improved. High-speed serial link technology has gradually replaced the traditional parallel transmission, such as HDMI, Displayport, USB, SATA, PCI-Express. However, the attenuation of the data through the transmission channel is more serious, because the channel bandwidth does not increase accordingly. Therefore, the equalizer is widely used at receiver to compensate the data to increase the signal integrity. This thesis proposed a feed-forward equalizer at the receiver, the inter-symbol-interference (ISI) can be eliminated by using the analog delay circuit to delay the input signal, and multiplies a weight coefficient. Compared with the traditional architecture, it does not need to use the clock for sampling and buffer circuits, so the power consumption can be reduced while maintaining the data amplitude. In addition, the continuous time linear equalizer (CTLE)、 feed-forward equalizer (FFE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are be used in data compensation. As the result, the proposed adaptive receiver system not only reduce the complexity of hardware and power consumption, but also can be widely used for 7-33 dB channel loss application. This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 10 Gb/s PRBS7 NRZ data, and the 10 GHz full rate clock be adopted. In 7-dB channel loss, 22 % improvement in eye height after compensation. In 33-dB channel loss, 47 % improvement in eye height after compensation. The overall power consumption of whole receiver consumes 18.88 mW at 0.9 V supply voltage. The chip area with 40 nm which is scaling down by 45 nm is 1.060 mm2 and core area is 0.026 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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