應用於具資料保留錯誤之動態隨機存取記憶體的良率及可靠度提升技術;Yield and Reliability Enhancement Techniques for DRAMs with Data Retention Faults

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Title:	應用於具資料保留錯誤之動態隨機存取記憶體的良率及可靠度提升技術;Yield and Reliability Enhancement Techniques for DRAMs with Data Retention Faults
Authors:	杜宇平;Tu, Yu-Ping
Contributors:	電機工程學系
Keywords:	動態隨機存取記憶體;內建自我修復;錯誤更正碼;可變保留錯誤;DRAM;BISR;ECC;VRF
Date:	2023-02-02
Issue Date:	2023-05-09 18:13:43 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著動態隨機存取記憶體(DRAM)密度的快速成長，良率和可靠度成為DRAM大量生產的關鍵挑戰。修復和錯誤更正碼(ECC)是兩種廣泛使用來提升DRAM良率和可靠度的技術。然而，現今的DRAM有越來越多的可變保留錯誤(VRF)，這對修復和ECC的效果產生了嚴重影響。在此篇論文中，我們提出了內建自我修復(BISR)和基於ECC的錯誤區分技術來應對VRF造成的影響。我們基於ESP演算法提出了一種具單錯誤跳過(SF-skipping)的內建冗餘分析演算法(BIRA)，以改善VRF造成的低效冗餘分配。模擬結果指出即使ESP演算法達到近乎理想的修復率，在晶圓級(wafer-level)和封裝後(post-package)有卜瓦松(Poisson distribution)均值1.0∼5.0和0.2∼1.0的缺陷植入到四個具有3~7個冗餘之8K×128記憶體的條件下，我們的方法仍有約0.02∼1.15%的修復率提升。使用TSMC 90nm製程的硬體實現結果顯示當記憶體容量為500Mb時，所提出的方法有0.22%的硬體開銷。我們也提出了一種基於ECC的錯誤區分方法用於提高可靠度。透過用合適的資源修復每種錯誤類型，錯誤累積的機率就會降低並提高可靠度。模擬結果指出在每秒錯誤率為1.2×10-11∼1.25×10-11之128K×16記憶體的條件下，我們的方法以約0.8∼2.5%的性能開銷使故障前平均時間(MTTF)達到560.9~991.6天。;As the rapid growth of the dynamic random access memory (DRAM) density, yield and reliability have become critical challenges for the mass production of DRAMs. Repair and error correction code (ECC) techniques are two widely used yield and reliability enhancement techniques for DRAMs. However, modern DRAMs have more and more variable retention faults (VRFs) which having a heavy impact on the efficiency of repair and ECC. In this thesis, we propose built-in self-repair (BISR) and ECC-based fault distinguishing techniques to cope with the impact caused by VRFs. A built-in redundancy analysis (BIRA) algorithm with single-fault skipping (SF-skipping) method based on essential spare pivoting (ESP) algorithm is proposed to improve the ineffective allocation caused by VRFs. Simulation results show that the proposed method has about 0.02∼1.15% increment of repair rate even if the ESP algorithm reaches nearly optimal repair rate, while defects with Poisson distribution mean value 1.0∼5.0 and 0.2∼1.0 for wafer-level and post-package repair are injected to four 8K×128 memory banks with 3∼7 spares. The BISR hardware implementation results using TSMC 90nm library show that the hardware overhead of the proposed method is 0.22% while the memory size is 500Mb. An ECC-based fault distinguish method is also proposed for in-field reliability enhancement. By repairing each fault type with appropriate resources, the probability of fault accumulation is reduced and the reliability can be improved. The simulation results show that the mean time to failure (MTTF) of the proposed method is 560.9∼991.6 days with the performance overhead about 0.8∼2.5%, while the average fault rate of a 128K×16 memory bank with 1∼10 spares is 1.2×10^(−11)∼1.25×10^(−11) per second.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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