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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9091


    Title: 深次微米金氧半場效應電晶體元件特性分析暨大訊號模型及其在高頻電路之應用;The Characteristics and Modeling of the Deep Sub-micron CMOS Device and Applications for RF Circuits Design
    Authors: 何建志;Chien-Chih Ho
    Contributors: 電機工程研究所
    Keywords: 金氧半場效應電晶體;Modeling;CMOS
    Date: 2004-09-29
    Issue Date: 2009-09-22 11:40:56 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 隨著先進製程之蓬勃發展,金氧半場效應電晶體的尺寸已縮小至奈米級,而較低的製作成本及可將數位和類比電路整合於同一基板的優點使得互補式金氧半場效應電晶體更有吸引力。由於電晶體閘極長度之持續縮減使其在高頻特性獲得大幅的改善,因此矽質互補式金氧半場效應電晶體已被廣泛的建議並使用於無線收發電路。為了達到這些目標,一個準確的元件模型以及詳細的元件特性分析對電路設計者而言是非常重要的。 首先在第二章裡,儘管p型金氧半場效應電晶體有低遷移率的缺點,但其也擁有較低的閃爍雜訊及熱載子效應等優點,可供高頻電路設計另一個極佳的應用解決方案,因此我們以傳統的BSIM3v3大訊號模型為基礎,加上其寄生效應的影響,建立一個0.18微米p型金氧半場效應電晶體高頻大訊號模型,此一大訊號模型可準確模擬元件的直流、高頻與功率特性。並設計一個操作在2.4 GHz之p型金氧半場效應電晶體壓控振盪器作為驗證。 於第三章中,我們針對0.13微米 n型金氧半場效應電晶體做出自我定義的大訊號模型。此利用經驗與數學模式組成的大訊號模型不僅可以精準的預測元件的直流、高頻特性與高功率輸入輸出的行為,且經過雜訊參數P、R、C的逼近後,可以預測此場效應電晶體的雜訊指數。除了需要簡單且準確的元件模型,在本章中將會探討0.13微米電晶體的閘極佈局方式對於元件之高頻與高功率特性,另外,也會研究壓控變容器的閘極佈局方式對其調變範圍與品質因數之影響。 對於射頻電路應用而言,除了元件之高頻及功率特性以外,另一個重要的參數為雜訊特性,元件的低頻閃爍雜訊與高頻熱雜訊對於電路設計皆有關鍵的影響。在第四章中,將會討論電晶體的閘極佈局方式對於元件之雜訊特性的影響,包含相同閘極寬度不同佈局方式、不同閘極寬度、不同閘極長度等方式來探討;並利用不同閘極佈局方式之0.13微米電晶體,實現於5.2 GHz壓控振盪器以討論元件雜訊對於振盪器電路之相位雜訊的影響,其FOM值可改善至–182 dBc/Hz。 在第五章中,利用自行建立之金氧半場效應電晶體高頻大訊號模型來設計不同的0.18微米高頻電路,包含2.4 GHz低相位雜訊p型電晶體壓控振盪器、2.4 GHz/5.2 GHz雙模壓控振盪器、高功率附加效益E類放大器。在p型電晶體壓控振盪器方面,利用p型電晶體組成反轉型壓控變容器並結合螺旋型電感達到在2.4 GHz的振盪頻率下,其相位雜訊在100 KHz的偏移下可低至–101 dBc/Hz且FOM值為–177 dBc/Hz。在雙模壓控振盪器方面,利用控制開關式電晶體之偏壓,調整振盪源使其可操作在2.4 GHz與5.2 GHz之應用。在改善功率附加效益放大器的電路中,使用E類放大器之設計使電壓與電流在同一時間週期內反相,以節省直流功率損耗,此E類放大器於2.4 GHz操作下可提供17.3 dBm輸出功率且功率附加效益為63 %,此外,結合F類驅動級之E類放大器可使波形更理想,並將功率附加效益提升至70 %。 With the technological advances, the MOS device size was already scaling down to the nano dimension. The low cost of fabrication and the possibility of placing both analog and digital circuits on the same chip so as to improve the overall performance made CMOS technology attractive. The scaling down of device improves the speed of MOSFETs significantly and hence the silicon CMOS technologies have been widely recommended and used in the wireless front-end transceiver for its high integration level, low cost, and potential of low-power operation. To achieve these goals, the accurate device model and detailed device characteristics are important for the circuit designers. Although, the p-channel MOSFETs suffer for their low transport properties; however, the lower 1/f noise level and less hot carrier effect in pMOS may provide an unique solution in microwave circuit design. Therefore, in order to design a rf circuit based on the pMOS, a modified 0.18 ?m pMOS rf large-signal model based on conventional BSIM3v3 model is proposed in the Chapter II, which demonstrated a well prediction of the dc, S-parameters, large-signal characteristics and power performance. We also designed a 2.4 GHz fully integrated pMOS voltage-controlled oscillator to verify our modified rf large-signal model. In the Chapter IΙI, a self-defined large-signal model for 0.13 ?m nMOS transistor is proposed. The self-defined model can predict not only dc and microwave performance well but also in noise characteristics by using P, R, C noise parameters calculation. Besides the simplified and accurate model of the device is needed, the optimum gate layout of 0.13 ?m transistors for high frequency and power application becomes a critical issue, which is also investigated in this chapter. In addition, the optimum gate layout of n+/n-well MOS varactor for the tuning range and Q factor improvement is also studied in this chapter. Besides the 0.13 ?m device high frequency and power performances, one of the key features of a technology platform for rf applications is the noise performance, particularly for front-end receiver functions. The noise performance of the optimized gate layout structure in constant total gate-width devices, different gate length and gate width devices are investigated in Chapter IV. We also design two VCOs by different gate layout MOSFETs to verify the phase noise influence from device layout structure. In the Chapter V, various rf circuits are presented based on the home-made modified rf large-signal model and implemented by 0.18 ?m CMOS technologies, which include low phase noise 2.4 GHz fully integrated pMOS VCO, 2.4 GHz/5.2 GHz dual-band VCO and high power-added efficiency class-E amplifier. The pMOS VCO including inversion-mode varactors and on-chip spiral inductors, achieves an excellent phase noise of –101 dBc/Hz at a 100 KHz offset and figure-of-merit of –177 dBc/Hz. In the dual-band VCO design, the switching transistors concept used in the tank circuit realizes the dual-band VCO operation, which provides the oscillation frequency bands for both 2.4 GHz and 5.2 GHz applications. In the efficient amplifier design, the switching operating mode class-E amplifier delivers 17.3 dBm output power at 2.4 GHz, with a maximum PAE of 63% from a 2-V supply voltage. Furthermore, the class-E amplifier with a class-F driver stage demonstrates the improved maximum PAE of 70%.
    Appears in Collections:[電機工程研究所] 博碩士論文

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