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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9221

    Title: 2.5Gbps光纖收發機設計;2.5Gbps Optical Transceiver
    Authors: 呂昭信;Chao-Hsin Lu
    Contributors: 電機工程研究所
    Keywords: 相位鎖相迴路;光纖;收發機;接收器;資料回覆器;傳送器;Phase-Locked Loop;Optical;Transceiver;Receiver;Data Recovery;Transmitter
    Date: 2001-06-19
    Issue Date: 2009-09-22 11:43:25 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 光纖網路應用在高速和長程傳輸通訊已經變成一個主要的趨勢。傳統上,光纖收發機是使用昂貴的砷化鉀製程。今日,數GHz的射頻ICs已經成功的使用次微米的CMOS和BicMOS製程來達到。而以加快降低光纖元件的成本為目標,本篇論文探討使用矽製程來達成光纖收發機的電路設計技術。以及研究的目的是為了達到2.5Gbps的光纖收發機電路。 在傳送器端,一個2伏、2.5Gbps的CMOS資料合成器被提出。高速的平行至串列的轉換是使用一個低抖動和八個相位的PLL來做以時間區分的多工器。其最大的轉換速率超過了312.5Mbytes/s。更進一步地,一個雷射驅動器被使用來驅動一個外加的雷射電晶體。其製作在0.8mm BiCMOS的製程,可達到30mA調變電流、10mA偏壓電流和操作在3Gbps下。經量測的結果,其眼圖符合OC-48的要求。 接收器的前端ICs發展在這一次的工作之中,包含了一個轉阻放大器和一個限制放大器,它們是利用0.35mm CMOS製程來達到,且操作在3V的電壓下。轉阻放大器提供一個54dBW和2.5GHz的-3dB頻寬。而限制放大器則是有4mv的敏感度、2.2GHz的-3dB頻寬和40dB的增益。另外,再提出一個使用3倍取樣技術的資料回覆器電路。 所有在這篇論文中所提出之電路皆有完整的探討和測量。其效能大大地顯視出未來光纖通訊在CMOS製程上SoC化的可行性。 Optical networking has become a main stream for high speed and long haul data communication. Conventionally, optical transceivers are implemented in expensive GaAs process. Nowadays, multi-GHz RF ICs in deep submicron CMOS and BiCMOS process have been successively demonstrated. With the aim at accelerating the cost-down of optical communication devices, this thesis explores circuit techniques for optical transceiver design in Si-based IC technologies. The objective goals of this research are to realize 2.5Gbps optical transceiver ICs. At the transmitter side, a 2V and 2.5Gbps CMOS data serializer has been proposed. High speed parallel to serial data conversion is achieved by means of time-division multiplexer toggled by a low jitter and 8-phases PLL. The maximum conversion rate is in excess of 312.5Mbyte/sec. Moreover, a laser diode driver in the succeeding stage has been implemented to drive an external laser diode. Fabricated in a 0.8mm BiCMOS process; the driver circuit delivers a modulation current of 30mA, a biased current of 10mA and is capable of operating at 3Gbps. The measured eye diagram meets the transition mask required by OC-48. The front-end ICs at the receiver side developed in this work include a transimpedance amplifier (TIA) and a limiting amplifier (LA), which are implemented in 0.35mm CMOS technology and operated under a 3V supply. The TIA provides a conversion gain of 54dBW with a —3dB bandwidth of 2.5GHz. The limiting amplifier achieves an input sensitivity of 4mv, -3dB bandwidth of 2.2GHz and conversion gain of 40dB. In addition, an oversampling by three data recovery circuits architecture has been proposed. All the circuit blocks described in this thesis have been thoroughly investigated and measured. The promising performances demonstrated strong potentials for future SoC solutions of optical transceivers in CMOS technology.
    Appears in Collections:[電機工程研究所] 博碩士論文

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