| 摘要: | 向量旋轉（Vector Rotation）在數位信號處理中扮演著重要的角色，並且已經廣泛應用於許多數位信號處理的系統中，舉凡在非連續性正交轉換、數位晶格濾波器以及數位頻率合成器中，皆佔有舉足輕重的地位。然而，我們若直接用乘法器及加法器來實現向量旋轉則將耗費太多的硬體。於是，開發設計一個低成本且又高效率的向量旋轉器矽智產來取代是必要的。 數位座標旋轉器演算法(CORDIC Algorithm)是實現向量旋轉的一個好方法。在回顧一些CORDIC演算法之後，我們選擇了有具有低成本、高精確度及高速優點的擴展基本角度集合的CORDIC (EEAS-CORDIC)，並搭配前置旋轉的機制來達到更好的效能。 在現實的部分，我們針對關鍵的電路做深入的探討並在細節部分像是物理層級的改良以及係數方面的安排，都有仔細的考量。為了掌控我們的品質，我們採用全客戶流程設計來將我們的設計最佳化。在細部的設計中，我們使用的pass-nmos 邏輯的方式來實現滾桶式位移器以降低硬體上面積的耗費。模式選擇器的設計取代了原有的多工器來選擇不同的模式，這樣的設計不但可以比原來的設計減少大約13%的拉線面績，並且具備前置旋轉的功能。在加減法器部分我們則是利用了Carry Save Adder 與Carry Look-ahead Adder的技巧來提高我們EEAS- CORDIC IP的效能。另外，測試考量也包含在EEAS- CORDIC IP設計之中。我們採用台積電0.35um 1P4M CMOS的製程，而我們所設計出EEAS-CORDIC的矽智產核心面積只有0.133平方厘米並具有16位元的精確度。由後期模擬 (Post-simulation) 可知，EEAS-CORDIC矽智產可以操作在150MHz的工作頻率。相較於標準式元件設計，要比我們的設計多花上近6倍的硬體才能達到相同的速度要求。 Vector rotation plays an important role in many Digital Signal Processing (DSP) systems, such as discrete orthogonal transform, lattice-based digital filter, and direct digital frequency synthesizer. However, it is not a cost-efficient way to realize the vector rotation directly with multipliers and adders. Instead, a well-designed, cost-efficient, and high-performance vector rotator IP is necessary. COordinate Rotational DIgital Computer (CORDIC) algorithm is a well-known technique to perform the rotational operation in digital arithmetic. After reviewing some CORDIC algorithms, we choose Extended Elementary Angle Set (EEAS) due to its characteristic of low-complexity, high precision, and high speed. Besides, pre-rotation scheme can help us improve the performance of EEAS-CORDIC in advanced. In the part of implementing the key components, we make a discussion for delicate design issues, such as physical improvements and parameters arrangements. In order to cost down the hardware complexity, we use pass-nmos logic technique to implement barrel shifters. We develop mode selectors to control the operation mode, and save about 13% area for wiring in original design. Besides mode selectors provide the function for pre-rotation scheme without any other redundant hardware cost. In part of adder/subtractor design, we use the technique of carry save adder and carry look-ahead adder to improve the performance of our EEAS-CORDIC IP. Testing issues, however, are also considered in our design. In order to guarantee the quality of our EEAS-CORDIC IP, we use full custom design flow to optimize our design. The IP is fabricated in tsmc 0.35um 1P4M CMOS process, and the core area of EEAS-CORDIC with 16-bit precision is only 0.133 mm*mm. The post-simulation shows the IP can be operated at 150MHz of clock rate using 3V supply voltage. Compared with standard cell design, standard cell spend about 6 times of cost under the similar timing condition. |
