English  |  正體中文  |  简体中文  |  Items with full text/Total items : 66984/66984 (100%)
Visitors : 22654747      Online Users : 335
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9276


    Title: 多模組相位同步技術;Multi-module synchronization methodology
    Authors: 麥世達;Shi-Dai Mai
    Contributors: 電機工程研究所
    Keywords: 鎖相迴路;自動測試機台;同步;PLL;ATE;synchronization
    Date: 2002-07-05
    Issue Date: 2009-09-22 11:44:29 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 在此論文中,我們提出兩種多模組相位同步技術。第一種同步架構主要描述板子上的多模組相位同步問題。第二種同步架構主要描述單一晶片的多模組相位同步問題。這兩種同步技術目前是適合應用於整合自動測試機臺的多通道時序同步問題及大型SOC系統的環境。我們利用微調相位機制去減少模組間的時序誤差(timing skews)並提供一穩定的相位。兩種架構分藉由TSMC 0.35 µm 1P4M CMOS 和 TSMC 0.18 µm 1P6M的製程技術設計製作。電路最高工作頻率分別為200MHz 及1GHz。在架構一的量測結果,再初始時序誤差800ps及抖動( clock jitter)50ps的條件下,板子上的五個模組的相位誤差可拉近至100ps以內。在架構二的模擬結果,再初始時序誤差800ps及抖動( clock jitter)20ps的條件下,單一晶片內的五個模組的相位誤差可拉近至80ps以內。 In this thesis, we propose two novel multi-module synchronization mechanisms. The first architecture describes a board level multiple modules synchronization. The second architecture describes an on-chip multiple modules synchronization. The two techniques target the synchronization for test channels in automatic test equipment (ATE) and system on a chip (SOC) environment respectively. We utilize fine tune mechanisms to suppress timing skews between modules and provide the highly stable phase. Both multi-module synchronization are based on TSMC 0.35 µm 1P4M CMOS and TSMC 0.18 µm 1P6M CMOS processes respectively. The results are at 200MHz and 1GHz respectively. The measurement and simulation results show that on-board architecture is capable of reducing the skew of the five modules to less than 100ps and the clock frequency up to 200MHz with 50ps clock jitter when the initial skew of each module is as large as 800ps. The simulation results also show that on-chip architecture reduces the skew of the five modules to less than 80ps and the clock frequency up to 1GHz with 20ps clock jitter when the initial skew of each module is as large as 800ps
    Appears in Collections:[電機工程研究所] 博碩士論文

    Files in This Item:

    File SizeFormat
    0KbUnknown679View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明