| 摘要: | 隨著現今科技的發展和普及，人們對網路的依賴性也愈來愈高，且對裝置或設備的傳輸速度需求也日漸提高，而在高速乙太網路傳輸系統中，如2.5GBASE-T或 5GBASE-T系統，消除迴音干擾是一個重要議題。傳統的迴音消除器常以數位電路實現，而迴音通道響應可以分成若干段，其最大值落於最前段，若在此數位迴音消除器中加入類比迴音消除器，則可以將此最大值在進入數位電路前先行消除，達成減少後續數位電路位元數的效果，而此類比迴音消除器中，需要一個類比演算法電路來提供類比濾波器之係數。
本論文根據IEEE 802.3bz™-2016 規範標準，實現一類比最小均方演算法電路，並且主要分為乘法器電路與積分器電路兩個部分，前者採用吉爾伯特單元(Gilbert cell)作為演算法之乘法器，實現類比輸入之係數和類比輸入之資料相乘功能，並配合系統環境之輸入擺幅，在提高輸入擺幅的同時，也能兼顧線性度方面的表現；後者之架構則為切換式電容(Switched-capacitor)積分器，實現演算法之加法功能與係數儲存之作用，調整乘法器之增益和積分器之回授電容與積分電容的比例，可以決定此演算法電路之步階值(Step size)，並且以全差動電路架構實現之，可以降低製程偏移、電壓偏移與溫度對系統之影響，使電路有較好的誤差表現。
本論文採用TSMC 40nm CMOS標準製程，晶片面積約為0.25mm¬¬2¬(包含I/O PAD)，電源電壓為2.5V和0.9V，操作頻率為200MHz，核心電路功耗約為3.21mW，而整體電路之平均誤差為-47.31dB。
;With the development and popularization of today′s technology, people′s dependence on the network is getting higher, and the demand for transmission speed of devices or equipment is also increasing. In high-speed Ethernet transmission systems, such as 2.5GBASE-T or 5GBASE-T system, eliminating echo interference is an important issue. Traditional echo cancellers are often implemented with digital circuits, and the echo channel response can be divided into several segments, the maximum value of echo channel response falls at the forefront. If an analog echo canceller is added to the traditional digital echo canceller, the maximum value can be eliminated before entering the digital circuit to achieve the effect of reducing the number of bits in the subsequent digital circuit. In this analog echo canceller, an analog algorithm circuit is required to provide the coefficients of the analog filter.
According to the IEEE 802.3bz™-2016 specification standard, this thesis presents a design of an analog Least Mean Square algorithm circuit, which is composed of into two parts: a multiplier circuit and an integrator circuit. The former uses the architecture of Gilbert cell as the multiplier of the algorithm to realize the multiplication function of the analog coefficient input and the analog data input, and adjust the input swing based on the system environment, while improving the input swing, it can also have a good the performance of linearity; the latter uses a switched-capacitor integrator, which realizes the addition function of the algorithm and the function of coefficient storage. Adjusting the gain of the multiplier and the ratio of the feedback capacitor of the integrator to integral capacitor of the integrator can determine the step size of the algorithm circuit, and realize this design with a fully differential architecture can reduce the influence of process deviation, voltage deviation and temperature on the system, so that this design has better performance of error value.
This circuits are designed in TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V, the chip area is 0.25mm2 (including I/O PAD), the supply voltage is 2.5V and 0.9V, the operating frequency is 200MHz, and the power consumption of the core circuit is 3.21mW. Finally, the average error of the whole chip is -47.31dB. |
