本論文探討使用較為節省記憶體空間的分離法等效電路在半導體元件模擬上的效益。分離法分離我們所使用半導體上的三組等效電路並且依序計算處理，三組等效電路是由三個描述半導體電性的偏微方方程式所轉換而成。透過模擬雙載子電晶體及金氧半場效電晶體來比較分離法與聯合法的計算效率及準確性，結果顯示分離法使用較少的記憶體空間，是聯合法的九分之一，而且得到的模擬結果是相同的，在模擬金氧半場效電晶體的次臨限電壓區域，及雙載子電晶體的低注入區域的電壓電流時，分離法比聯合法有較快的速度。在混階模擬方面，我們也提出部分分離法，它具有聯合法九分之四的記憶體空間，而且擁有完整的邊界條件可用於混階模擬上。 In this thesis, we study the decoupled method which requires less memory on semiconductor device simulation. The decoupled method decoupled the three equivalent circuits of semiconductor and solved them sequentially. The three equivalent circuits are formed by formulating the three partial differential equations which describe the electrical behavior of semiconductor. The decoupled method is compared by coupled method for computational efficiency and accuracy in simulation of BJT and MOSFET. Results show the decoupled method uses one-ninth memory space of the coupled method. The simulation results are identical. Decoupled method are faster than coupled method when simulating in subthreshold region of MOSFET and low level injection of BJT. In mixed-level simulation, we propose a compromising partial decoupled method which requires four-ninths memory space of the coupled method and has complete boundary condition for mixed-level simulation.
