適用於頻域雷達回波訊號壓縮之可適性區塊量化器設計;Design of Block Adaptive Quantizer for Radar Echo Signal Compression in Frequency Domain

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题名:	適用於頻域雷達回波訊號壓縮之可適性區塊量化器設計;Design of Block Adaptive Quantizer for Radar Echo Signal Compression in Frequency Domain
作者:	尤泓澍;Yu, Hung-Shu
贡献者:	電機工程學系
关键词:	可適性區塊量化器;合成孔徑雷達;資料壓縮;快速傅立葉轉換;block adaptive quantizer;synthetic aperture radar;data compression;fast Fourier transform
日期:	2023-08-11
上传时间:	2024-09-19 17:02:00 (UTC+8)
出版者:	國立中央大學
摘要:	隨著地表遙測與探勘的需求，雷達影像的解析度日益提升，意味著需要傳送的雷達影像資料量也隨之增加，然而太空中的衛星與地面上的基地站之間的通道傳輸容量有限，為了解決此問題帶來的影響，影像資料壓縮的技術成為了不可或缺的一環。本論文主要探討適用於合成孔徑雷達(Synthetic Aperture Radar, SAR)的影像資料壓縮技術，稱為可適性區塊量化器(Block Adaptive Quantizer, BAQ)，並進一步深入研究於頻域上的BAQ 影像資料壓縮演算法，稱之為快速傅立葉轉換之可適性區塊量化(Block Adaptive Quantizer with Fast Fourier Transform, FFT-BAQ)；相較於傳統時域上的BAQ 系統，FFT-BAQ 會將雷達影像資料轉到頻域上，且只需要壓縮並傳輸頻寬內的資料，因此比起傳統時域上的BAQ演算法FFT-BAQ 能節省更多的資料量，而本論文會基於FFT-BAQ 的概念，設計改良的FFTBAQ系統架構，此架構在原本的FFT-BAQ 系統上加入並整合零填充(Zero padding) 、漢明窗(Hamming window)與循環重複(Cyclic duplicate)的訊號處理動作，藉此達到最佳的量化壓縮效能。接著本論文會提出一個基於記憶體之可重構式多重路徑延遲交換FFT 架構，提供給我們提出的改良後的頻域FFT-BAQ 系統架構使用，FFT 架構中的可重構之處理單元(Processing element)可支援Radix-4、Radix-8、Radix-4^2、Radix-3、Radix-3^2與Radix-5 共六種不同模式的運算，除此之外，藉由使用位移器與加法器取代處理單元內瑣碎旋轉因子(trivial twiddle factor)乘法器，可以降低架構所需要的硬體資源，最後會使用硬體描述語言將可重構的多重路徑延遲交換處理單元架構實現，其操作頻率最快可執行到200MHz。;With the demand for high-resolution images, the data quantity of radar echo signals becomes large. However, the channel capacity between satellites in the space and base stations on the ground is limited. In order to solve this problem, data compression is necessary.In this thesis, data compression technique suitable for synthetic aperture radar is studied, including conventional block adaptive quantizer (BAQ) in the time domain, and data compression in frequency domain, called block adaptive quantizer with fast Fourier transform(FFT-BAQ). Since FFT-BAQ only compresses and transmits the data inside the chirp bandwidth, fewer data are transmitted. Based on the concept of FFT-BAQ, we design an improved FFT-BAQ architecture, which integrates zero padding, Hamming window and cyclic extension to the original FFT-BAQ system to enhance the quantization performance when practical FFT hardware accelerator is used. Then, a memory-based reconfigurable multi-path delay commutator FFT architecture is designed for our improved frequency-domain FFT-BAQ system. The reconfigurable processing element can support six different modes including Radix-4、Radix-8、Radix-4^2、Radix-3、Radix-3^2 and Radix-5. In addition, the trivial twiddle-factor multipliers of the reconfigurable PE are replaced by shifters and adders, so the hardware resources required by the FFT architecture is reduced. Finally, we use the hardware description language to implement the reconfigurable multi-path delay commutator processing element ,which can operate at a maximum operating frequency of 200 MHz.
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