| 摘要: | 毫米波頻段中的 Q 頻段（33—50.5 GHz），因其有較大的頻寬、
更快的傳輸速率以及更短的延遲，在近年來被廣泛應用。Q 頻段的應
用包括氣象雷達、第五代行動通訊以及新興的衛星網際網路。不管在
以上任何應用，相位陣列在收發機架構中都是不可或缺的。而相位偏
移器在相位陣列中扮演著最重要的角色，藉由提供可調變的相位差給
相位陣列中的天線，來改變相位陣列發射與接收的方向。
在第二章中，我們使用 TSMC 90-nm CMOS 製程來設計，電路
的中心頻為 35 GHz。以五級的數位式相移級組合成一 Ka 頻段五位元
被動式相位偏移器。其中 11.25°、22.5°、45° 及 90° 相位偏移器都是
使用傳輸線基準全通網路架構。180° 相位偏移器則是使用一對單刀雙
擲開關（single-pole double-throw, SPDT）實現。由量測結果來看，
均方根相位誤差在 4° 以內對應到的頻率範圍是 32—42.7 GHz，頻寬可
達 28.64%；在頻寬內返回損耗大於 10.8 dB，植入損耗小於 15 dB；
振幅誤差為 ±0.7 dB 以內。
在第三章中，我們使用 TSMC 90-nm CMOS 製程來設計，電路
的中心頻為 35 GHz。以五級的數位式相移級組合成一 Ka 頻段五位元
被動式寬頻相位偏移器。11.25°、22.5°、45° 及 90° 相位偏移器都是使
用傳輸線基準全通網路架構。其中為了增加頻寬，90° 相位偏移器是
以兩個中心頻錯開的傳輸線基準全通網路合成一級相移級。180° 相位
偏移器則是使用一對 SPDT 實現。由量測結果來看，均方根相位誤差
在 4° 下所對應到的頻寬為 29—45.1 GHz，頻寬可達 43.45%；在頻寬
內返回損耗大於 10.4 dB，植入損耗小於 17.9 dB；振幅誤差為 ±0.55 dB 以內。
在第四章中，我們使用 TSMC 90-nm CMOS 製程來設計，電路
的中心頻為 38 GHz。為了降低電路的損耗，我們以一級的類比式
相移器取代三級的數位式相移器，再接上 90°、45° 數位式相移器來
組合成一 Q 頻段五位元 180° 被動式相位偏移器。其中為了增加頻
寬，90°、45° 相位偏移器分別是以兩個中心頻錯開的傳輸線基準全
通網路合成一級相移級。類比式相移級我們使用 MOS varactor 來
實現可變電容，再搭配 3-bit 的數位電位器（digital potentialmeter,
DPOT）來讓類比式相移級可以用數位的方式來控制，進而取代原
本的 5.625°、11.25°、22.5° 數位式相位偏移器。由量測結果來看，均
方根相位誤差比模擬結果來的大，在均方根相位誤差 4° 以下所對應
到的頻寬為 36—48.5 GHz，頻寬可達 29.58%，在頻寬內返回損耗大於
13.5 dB，植入損耗小於 18.3 dB；振幅誤差為 ±0.75 dB 以內。而均
方根相位誤差在 5° 以下所對應到的頻寬為 27.2—51.3 GHz，頻寬可達 61.4%；在頻寬內返回損耗大於 13.5 dB，植入損耗小於 18.3 dB；振
幅誤差為 ±1.1 dB 以內。
在本論文中，我們成功實現了使用傳輸線基準全通網路之 Q 頻段
的 CMOS 180° 相位偏移器。透過以兩個中心頻錯開的傳輸線基準全
通網路合成一級相移級的方式，成功提升了電路的頻寬；又透過以一
級的類比式相移器取代三級的數位式相移器，來降低了電路的損耗，
成功達到 180° 相位偏移量以及六位元（5.625°）的相位解析度。
;The Q band in the millimeter-wave frequency range (33--50.5 GHz) has been widely applied in recent years due to its larger bandwidth, higher transmission speed, and shorter latency. Q band finds applications in meteorological radar, 5G mobile communications, and emerging satellite internet. Regardless of these applications, phased arrays play an indispensable role in the transmitter-receiver architecture, and phase shifters are crucial components within phased arrays. By providing adjustable phase differences to the antennas in the phased array, phase shifters enable the manipulation of the direction of transmission and reception.
In Chapter 2, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 35 GHz. A five-stage digital phase shifter was implemented to achieve a five-bit passive phase shifter in the Ka band. The phase shifters 11.25°、22.5°、45° and 90° , were all implemented using a transmission line-based quasi-all-pass network structure. The 180° phase shifter was realized using a single-pole, double-throw (SPDT) switch pair. Based on the measurement results, the root mean square phase error is within 4° with a bandwidth of 32 to 42.7 GHz, which corresponds to a bandwidth of 28.64\% ; the return loss is greater than 10.8 dB within the bandwidth, and the insertion loss is less than 15 dB. The amplitude error is within ±0.7 dB.
In Chapter 3, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 35 GHz. A five-stage digital phase shifter was combined to form a wideband five-bit passive phase shifter in the Ka band. The phase shifters, 11.25°, 22.5°, 45°, and 90°, were all implemented using a transmission line-based quasi-all-pass network structure. To increase the bandwidth, the 90° phase shifter was realized by combining two transmission line-based quasi-all-pass networks with center frequencies offset. The 180° phase shifter was implemented using an SPDT switch pair. Based on the measurement results, the root mean square phase error is within 4° with a bandwidth of 29 to 45.1 GHz, which corresponds to a bandwidth of 43.45\% ; the return loss is greater than 10.4 dB within the bandwidth, and the insertion loss is less than 17.9 dB. The amplitude error is within ±0.55 dB.
In Chapter 4, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 38 GHz. To reduce the circuit loss, we replaced the three-stage digital phase shifter with a single-stage analog phase shifter and combined it with the 45° and 90° digital phase shifters to form a five-bit passive phase shifter in the Q band. To increase the bandwidth, the 45° and 90° phase shifters were implemented by combining two transmission line-based quasi-all-pass networks with center frequencies offset. The analog phase shifter was implemented using MOS varactor to achieve variable capacitance and combined with a digital potentiometer (DPOT) controlled digitally, replacing the 5.625°, 11.25°, and 22.5° digital phase shifters. The measurement results showed that the root-mean-square phase error was larger than the simulation results. The root mean square phase error is within 4° with a bandwidth of 36 to 48.5 GHz, which corresponds to a bandwidth of 29.58\% ; the return loss is greater than 13.5 dB within the bandwidth, and the insertion loss is less than 18.3 dB. The amplitude error is within ±0.75 dB. The root mean square phase error is within 5° with a bandwidth of 27.2 to 51.3 GHz, which corresponds to a bandwidth of 61.4\% ; the return loss is greater than 13.5 dB within the bandwidth, and the insertion loss is less than 18.3 dB. The amplitude error is within ±1.1 dB.
In this thesis, we successfully implemented a CMOS phase shifter in the Q band using a transmission line-based quasi-all-pass network. By combining two transmission line-based quasi-all-pass networks with offset center frequencies to form a single-stage phase shifter, we achieved improved circuit bandwidth. By replacing the three-stage digital phase shifter with a single-stage analog phase shifter, we reduced circuit loss and achieved 180° phase shift resolution and six bits (5.625°) of phase resolution. |
