| 摘要: | 隨著近年雲端運算、邊緣運算、人工智慧等資通產業的蓬勃發展，其技術對運算需求快速提升，對資料傳輸速度與環境雜訊複雜度的要求也有所提升。然而高速串列傳輸速度提升，資料受到傳遞距離衰減影響越為嚴重，雜訊占總體訊號比例也隨所傳遞距離提升迅速放大，訊號品質因此下降，因此等化器如何使訊號在傳輸過程能還原其完整度就顯得十分重要。
本論文提出訊號自參考生成技術，以此來輔助單端輸入資料進行邏輯判斷，其利用資料振幅的電壓位準變換方向來判斷資料極性，並藉由所提出跟蹤-延續-再生比較器解決連續資料問題，實現自參考生成技術，以節省硬體複雜度並提升等化器對高雜訊環境的適應力，並搭配自適應系統，使等化器於高雜訊高通道衰減環境下，自參考生成技術都能輔助自適應系統與DFE對訊號進行合理的補償，並還原出正確的資料，使等化器在使用上能適用於更複雜之環境。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M之CMOS製程來實現，電路操作電壓為1 V，輸入之資料速率為10 Gbps之單端NRZ 資料訊號，輸入時脈採用單端5 GHz 時脈訊號，並藉由內部電路生成半速率差動5 GHz 時脈訊號，等化器於含有雜訊之使用環境最高可使用通道衰減為24dB，當輸入資料振幅為250mV時，最高可抵禦之低頻正弦波(100MHz)雜訊振幅為50mV，經自參考生成技術等化器還原後之資料速率為10 Gbps之單端NRZ 資料訊號，於佈局後模擬在通道衰減14 dB 時，還原後之資料抖動峰對峰值為27.63 ps；佈局後模擬在通道衰減24 dB時，還原後之資料抖動峰對峰值為22.51 ps。整體功率消耗為43.97 mW，其中等化器CTLE 、1-tap SR DFE與跟蹤-延續-再生比較器之功耗為19.73 mW，自適應系統之功耗為24.24 mW。整體面積為0.9×0.9 mm2，其中核心電路之面積約為0.103 mm2。
;With the rapid development of information and communication industries such as cloud computing, edge computing, and artificial intelligence in recent years, the demand for computing power has increased rapidly, and the requirements for data transmission speed and environmental noise complexity have also increased. However, as the transmission speed increases, the data is more seriously affected by the transmission distance, and the proportion of noise in the total signal also increases, resulting in a decrease in signal quality. Therefore, it is very important for equalizers to restore the integrity of the signal in the transmission process.
This paper proposes a signal Self-Reference generation technology to assist in the logical judgment of single-ended input data. It uses the voltage level change direction of the data amplitude to judge the data polarity. By using an innovative Track-Extend-Regenerate Slicer to solve the continuous data problem, the self-reference generation technology is realized to save hardware complexity and improve the adaptability of the equalizer to high-noise environments. In addition, it is combined with an adaptive system to ensure that the Self-Reference generation technology can assist the adaptive system and DFE to compensate the signal reasonably in high noise and high channel-loss environments, and restore the correct data.
This paper is implemented using TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operating voltage is 1 V. The input data rate is 10 Gbps single-ended NRZ data signal. The input clock adopts a single-ended 5 GHz clock signal, and a half-rate differential 5 GHz clock signal is generated by the internal circuit. The equalizer can be used in a noisy environment with a maximum channel-loss of 24 dB. When the input data amplitude is 250 mV, the maximum low-frequency sine wave (100 MHz) noise amplitude that can be resisted is 50 mV. After the signal Self-Reference generation technology equalizer restores the 10 Gbps single-ended NRZ data signal, the post-layout simulation shows that the peak-to-peak jitter of the restored data is 27.63 ps when the channel-loss is 14 dB. The post-layout simulation shows that the peak-to-peak jitter of the restored data is 22.51 ps when the channel-loss is 24 dB. The overall power consumption is 43.97 mW, of which the power consumption of the equalizer CTLE, 1-tap SR DFE, and Track-Extend-Regenerate Slicer is 19.73 mW, and the power consumption of the adaptive system is 24.24 mW. The overall area is 0.9 × 0.9 mm2, of which the area of the core circuit is approximately 0.103 mm2. |
