應用於第五代無線通訊之採用電流合成暨變壓器耦合技術互補式金氧半導體功率放大器研製;Implementations on CMOS Power Amplifiers Utilizing Current Combining and Transformer-Coupled Techniques for Fifth-Generation Wireless Communication Applications

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題名:	應用於第五代無線通訊之採用電流合成暨變壓器耦合技術互補式金氧半導體功率放大器研製;Implementations on CMOS Power Amplifiers Utilizing Current Combining and Transformer-Coupled Techniques for Fifth-Generation Wireless Communication Applications
作者:	翁彥琦;Weng, Yan-Qi
貢獻者:	電機工程學系
關鍵詞:	功率放大器;電流合成;磁耦合共振腔;Power Amplifier;Current Combining;Transformer
日期:	2024-01-26
上傳時間:	2024-03-05 17:56:37 (UTC+8)
出版者:	國立中央大學
摘要:	本論文使用台灣積體電路製造股份有限公司(tsmcTM ) 所提供之0.18-µm CMOS 1P6M製程，對於n77到n79頻段的功率放大器，採用兩種不同的功率合成技術，並透過濾波器的分析與變壓器的等效，分析匹配網路的損耗和構成條件，達成匹配網路的最佳化，實現功率放大器之設計。第一顆提出應用於n79頻段的單級電流合成式功率放大器，針對電流合成結構所帶來的低阻抗問題，透過選擇適當的電晶體尺寸，讓電晶體的輸出最佳負載阻抗，更貼近輸出匹配的阻抗點，使匹配網路更容易設計和製造。最終在4.4 - 5.0 GHz的頻段內最佳傳輸增益為12 dB，飽和輸出功率為27.1 dBm，功率附加效率最高可達16.5 %，晶片面積為 3.51 (2.02 × 1.73) mm2。第二顆提出應用於n77- n79頻段之使用二對一的變壓器匹配的功率放大器，使用特定的閘級偏壓及電晶體尺寸，將電晶體的輸出最佳負載阻抗，與輸出阻抗呈現特定的比例，以此實現二對一的變壓器匹配，並且透過特殊的電路佈局，降低變壓器匹配的寄生電容，也有效的壓縮匹配網路的電路面積，最終在3.6 - 5.6 GHz的頻段內，最佳傳輸增益為10 dB，飽和輸出功率為26 dBm，功率附加效率最高可達19.4 %，晶片面積為 2.22 (2.13 × 1.04) mm²。 ;This thesis utilizes the 0.18-µm CMOS 1P6M process provided by Taiwan Semiconductor Manufacturing Company (tsmc™). It investigates two distinct power combining techniques for power amplifiers operating within the n77 to n79 frequency bands. The analysis centers on filter and transformer topologies, delving into the loss and constituent conditions of the matching network to optimize its configuration, thereby facilitating the design of power amplifiers. The first proposed amplifier is a single-stage current combining power amplifier tailored for the n79 frequency band. To mitigate the low impedance challenges inherent in the current combining structure, appropriate transistor sizing is employed to optimize the transistor′s output load impedance, aligning it more closely with the impedance point of the output match. This approach makes the design and fabrication of the matching network easier. Ultimately, within the frequency range of 4.4 - 5.0 GHz, the achieved performance metrics include an optimal gain of 12 dB, a saturation output power of 27.1 dBm, and a peak power-added efficiency of 16.5%. The chip area measures 3.51 (2.02 × 1.73) mm². The subsequent proposed amplifier targets the n77 to n79 frequency bands, employing a two-to-one transformer matching approach. Through the utilization of specific gate bias and transistor sizes, the optimization of the transistor′s output load impedance is aimed at establishing a defined ratio with the output impedance, thereby achieving the intended two-to-one transformer matching. Additionally, a specialized circuit layout is implemented to reduce the parasitic capacitance associated with the transformer matching, effectively compacting the circuit area of the matching network. Ultimately, within the frequency range of 3.6 - 5.6 GHz, this configuration attains an optimal gain of 10 dB, a saturation output power of 26 dBm, and the highest power-added efficiency of 19.4%. The chip area measures 2.22 (2.13 × 1.04) mm².
顯示於類別:	[電機工程研究所] 博碩士論文

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