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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9452

    Title: 適用於通訊系統之參數化數位訊號處理器核心;Parameterized DSP Core for Communication System
    Authors: 曹亞嵐;YA-LAN TSAO
    Contributors: 電機工程研究所
    Keywords: 數位訊號處理;參數化架構;數位訊號處理器核心;DSP Processor;DSP;Parameterized Structure
    Date: 2005-07-08
    Issue Date: 2009-09-22 11:48:03 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 本文所撰述為適用於通訊系統之訊號處理器核心完整研究。整體研究包含處理器核心之參數化架構、多重功能之數據處理路徑、內嵌式系統之輸出入介面、低功率設計、可供選擇之特殊功能區塊、模組化訊號處理器核心產生器。 參數化數位訊號處理器核心是設計使核心針對不同應用需求有最佳化之效能。歸功於參數化架構,此數位訊號處理器核心可由使用者自行選定參數以適用所預定之系統。本論文所設定之適用系統為通訊系統。 本論文成功的建立完整設計流程,使數位訊號處理器核心有更彈性的設計特質以及更好的效能表現。 This thesis is a comprehensive work of a parameterized DSP core for embedded system. The overall research includes the parameterized architecture of the DSP core, multi-function data-path, input/output modes for embedded applications, low-power techniques, optional special function blocks and module generator. Parameterized DSP core is designed for optimal usage of different requirements in system applications. Owing to the parameterized structure, the DSP core can be custom made for dedicated system with parameters setting. The parameterized DSP core is especially suitable for an embedded system. The primary application is digital signal processing system which designed to achieve demodulation/synchronization with better performance and flexibility. We set up a novel design flow of embedded parameterized DSP core. The design flow includes a newly designed flexible parameterized DSP core structure, a module generator and a methodology to build the DSP core with optimal performance. The features in this DSP core include parameterized data-path, dual MAC unit, sub-word MAC and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low power structure, which includes the gray code addressing mode, pipeline sharing and a novel buffered hardware looping. Users can select the parameters and special function blocks based on the specification of their applications and then a synthesizable DSP core is generated in a proposed module generator with graph user interface. The proposed DSP core and the synthesizable RTL code have been verified with TSMC 0.35um SPQM, 0.25um 1P5M cell based and FPGA design flow.
    Appears in Collections:[電機工程研究所] 博碩士論文

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