| 摘要: | 氮化鋁鎵/氮化鎵異質接面的概念是於1991年正式被提出，並首次展現其對於電子移導率的改善。進而於1993年，第一個氮化鎵金半場效電晶體(MESFET)也被製作出來，而氮化鋁鎵/氮化鎵高速電子移導率場效電晶體(AlGaN/GaN HEMT)也於1996因應而生。而這一連串的發展速度相較於砷化鎵場效電晶體的發展速度幾乎快了10倍之多。當然這要歸功於先前砷化鎵半導體技術發展的基礎，但是更重要的是氮化鎵這類材料所擁有的先天優勢與特性，例如：高抗熱、高崩潰電壓、高電子飽和速度、優秀的壓電效應以及高電流密度等等。這些特性都讓氮化鎵場效電晶體在未來的高速和高功率的應用上成為極佳選擇。這也使得近年來世界上有相當多的人力著重與投入於氮化鎵場效電晶體的開發和研究。 相較於砷化鎵半導體技術發展，氮化鎵場效電晶體的開發依舊有相當程度的落後，其中最重要的不外忽是可分成磊晶與製程兩大類。磊晶方面最主要的問題來自於氮化鎵與基版高晶格位差(lattice mismatch)使得發展優良的緩衝層是必要的。而製程方面最重要的問題來自於高能隙帶氮化鎵類的半導體所衍生的高歐姆接觸、高壓電與極化特性所帶來的元件表面穩定度問題以及高功率所產生的熱效應等等。這些都是需要在氮化鎵場效電晶體的製程與分析上投入更多的研究來解決，否則，對於日後高功率元件的發展勢必成為瓶頸。 在本論文中，我們於第二章節中提出了高蝕刻選擇性與低表面損耗的電漿配方以應用於氮化鎵場效電晶體的製程。配合上我們在元件表面成長高n型參雜的氮化鎵做為表面層，我們可以利用此蝕刻技術來完成高穩定度的閘極絕入技術。進而使得我們能夠利用高n型參雜的氮化鎵的表面層來降低元件歐姆接觸而同時保留優秀的元件高崩潰電壓特性。在第三章中，針對氮化鎵場效電晶體的元件作更深入的延遲時間(delay time)分析。此分析可以顯示出元件各部分所展現的延遲，使我們可以更進一步的了解元件特性的瓶頸所在以便能夠針對其缺點做進一步的改善。在第四章中，我們引入了脈衝(pulse) I-V的檢測於氮化鎵場效電晶體來觀察其表面穩定與否。而同時我們引入了BCB此種低介電常數的物質做為元件的保護層以使元件在高頻操作時有更優良的表現。而透過脈衝(pulse) I-V的檢測也證明出此種材料在元件保護層的應用上是可行的。第五章中，我們利用電子束微影技術來針對氮化鎵場效電晶體的閘極做特別的改善，我們在不改變製程複雜度下，引入了Γ-型閘極來代替原有的T-型閘極。此技術可以降低元件表面的電場強度進而增加元件的崩潰電壓特性，而同時卻能保有類似的元件速度。而在最後的第六章中，我們針對大面積的氮化鎵場效電晶體做一系列的討論，首先我們對於元件特性與閘極寬度的關係上做一探討，並明顯觀察到嚴重的熱效應發生於大面積元件上。進而我們針對大面積的元件，來做不同閘極距離(gate pitch)的設計以希望能夠藉由分散元件的熱源來降低元件的熱效應。而我們也利用紅外線熱感測儀來偵測元件的溫度並配合元件的直流特性與微波特性做比較。而再最後一章的結論中整理之前章節的實驗結果與重點。 The AlGaN/GaN hetrostructure has been announced in 1991, and it has also been proven that the electron mobility of 2DEG could be indeed enhanced. Then the first GaN MESFET was delivered in 1993, and the first GaN HEMT was also fabricated in 1996, too. It is interesting that the developing speed of GaN HEMT was almost 10 times as the traditional AlGaAs/GaAs pHEMT. Except the successful experience of GaAs pHEMT, the excellent properties of GaN based materials are the key forces to push the research of GaN HEMT forward. The excellent properties of GaN HEMT such as high temperature stability, high breakdown voltage, high electron velocity, strong piezoelectric effect and high current density let the GaN HEMT be a good candidate for the applications of high speed and high power. In comparison with the development of GaAs pHEMT, there are a lot of issues in the research of GaN HEMT. The main problems can be divided into two fields, epitaxy and process. Owing to the lattice mismatch between the GaN and substrate, the research of how to improve the quality of GaN buffer layer is always an important and fundamental issue of GaN HEMT epitaxy. For the process issue, the high ohmic contact resistance caused by the wide bandgap property, the sensitive surface state, and the serious thermal effect are still under intensive study. In this dissertation, a high etching selectivity and low surface damage etching recipe for GaN/AlGaN hetrostructure was described in the chapter 2. After combining the design of using n+ GaN as the cap layer and the selective gate recess technology, a lower ohmic contact resistance and a fine breakdown characteristic can be expected. In the chapter 3, the delay time analysis was carried out to extract the distribution of delay times in the GaN HEMT and this discussion can help us understand which parts of delay times affect the device performance. In the chapter 4, the pulse I-V curves measurement system was setup to detect the status of device surface state. Then a new low-k material, BCB, was applied into the application of device passivation process. In comparison with traditional Si3N4 passivation layer, the BCB passivation layer provides a lower parasitic capacitance and a better rf performance. Additionally, the characterizations of pulse I-V and reliability test in BCB passivated GaN HEMT were also completed. In the chapter 5, the gamma gate engineering on GaN HEMT was successfully realized. Owing to the decrease of electric field strength, the gamma gate can enhance the device breakdown performance but the parasitic capacitance would not be obviously added. In the chapter 6, the heating effect in the power device was addressed and the various device layouts including various gate widths and various gate pitches were designed to discuss the relation between device layouts and heating effect. Then the thermal IR microscopy was used to detect the device surface temperature in various dc power consumptions and the thermal resistance could be obtained simultaneously. In the final chapter, we summarized the results obtained in this thesis. |
