| 摘要: | 在微波及毫米波接收機系統中，低雜訊放大器(LNA)為其前端關鍵積體電路。低雜訊放大器的主要功能是將天線接收之訊號放大後傳遞至下級電路。除了基本的增益與雜訊指數的要求外，低功耗與高線性度也是設計目標。在微波發射機系統中，功率放大器亦為其關鍵電路，隨著第五代通訊的發展成熟，位於毫米波頻段之高輸出功率放大器需求逐漸增加，高輸出功率與高線性度與寬頻之功率放大器相繼被提出，功率放大器在發射機系統通常為最耗電的元件，因此使用較低直流功耗與較節省面積的方式是功率放大器設計的趨勢。本論文的研究目標在低雜訊放大器方面期望能達到低功耗與高增益與高線性度為主，主要設計於K頻段與Ka頻段，並使用CMOS製程設計。功率放大器方面的研究目標則是以寬頻為設計目標，同樣設計於K頻段與Ka頻段，並使用CMOS製程設計。
第二章提出使用台積電90 nm製程設計的低雜訊放大器，該放大器操作於Ka頻段。為達到低功耗與高增益的特性，使用轉導提升架構與中和穩定電容架構，在提高增益的同時提高電路的穩定性，使用電流再利用架構以降低功耗，並以兩級架構實現。電路最大增益達到7.5 dB，最小雜訊指數為4.9 dB，晶片面積為0.37 mm2。
第三章提出使用台積電0.18 µm製程設計的低雜訊放大器，該放大器操作於K頻段。本次設計使用雙重變壓器架構以提升增益，使用源極退化電感以降低雜訊指數，同時透過在電晶體的Body端外接偏壓以改善線性度，另外同樣使用電流再利用架構以降低功耗。該電路以兩級疊接架構實現。電路最大增益為18.2 dB，最小雜訊指數為5.7 dB，晶片面積為0.53 mm2。
第四章分別提出使用台積電0.18 µm製程設計的功率放大器與台積電90 nm製程設計的功率放大器。使用台積電0.18 µm製程設計的功率放大器操作於K頻段，本次設計使用變壓器架構以達到增益寬頻的效果，該電路以兩級疊接架構組成。電路最大增益為19 dB，3 dB頻寬為20 GHz至26.1GHz，輸出1dB增益壓縮點為12.4 dBm，飽和輸出功率為16.1 dBm，輸出三階斷點為26 dBm。晶片面積為0.53 mm2。使用台積電90 nm製程設計的功率放大器則操作於Ka頻段，該電路設計以中和穩定電容架構提升電路的增益與穩定性，該電路以四路疊接架構組合而成。電路最大增益為12.5 dB，3 dB頻寬為28.3 GHz至42.6 GHz，輸出1dB增益壓縮點為10.3 dBm，飽和輸出功率為18.6 dBm，輸出三階斷點為20 dBm。晶片面積為0.49 mm2。
於論文的最後，第五章為本論文的總結。
;In microwave and millimeter-wave receiver systems, the Low Noise Amplifier (LNA) is a crucial integrated circuit at the front end. The primary function of the LNA is to amplify signals received by the antenna before transmitting them to the subsequent circuits. In addition to basic requirements such as gain and noise figure, low power consumption and high linearity are also design goals. In microwave transmitter systems, the Power Amplifier (PA) is another key circuit. With the development of fifth-generation communication, the demand for high-output power amplifiers in the millimeter-wave frequency band is gradually increasing. Amplifiers with high output power, high linearity, and wide bandwidth have been proposed. Power amplifiers are typically the most power-consuming components in transmitter systems, so designing them with lower DC power consumption and a more compact footprint is a trend.The research objectives of this thesis focus on achieving low power consumption, high gain, and high linearity for LNAs, primarily designed for the K-band and Ka-band using CMOS technology. For power amplifiers, the research goal is to achieve broadband performance, also designed for the K-band and Ka-band using CMOS technology.
Chapter 2 introduces a low noise amplifier designed using TSMC 90 nm process, operating in the Ka-band. To achieve low power consumption and high gain, a transconductance-boosting architecture and neutralization with stable capacitor architecture were employed to increase stability while improving gain. Current reuse architecture was used to reduce power consumption, implemented in a two-stage structure. The circuit achieved a maximum gain of 7.5 dB, a minimum noise figure of 4.9 dB, and a chip area of 0.37 mm2.
Chapter 3 presents a low noise amplifier designed using TSMC 0.18 µm process, operating in the K-band. The design utilizes a dual transformer architecture to enhance gain, source degeneration inductor to reduce noise figure, and an external bias on the transistor′s Body terminal to improve linearity. Additionally, a current reuse architecture was employed to reduce power consumption, implemented in a two-stage stacked structure. The circuit achieved a maximum gain of 18.2 dB, a minimum noise figure of 5.7 dB, and a chip area of 0.53 mm2.
Chapter 4 introduces power amplifiers designed using TSMC 0.18 µm and TSMC 90 nm processes. The power amplifier designed with TSMC 0.18 µm operates in the K-band, utilizing a transformer architecture to achieve broadband gain. The circuit, composed of a two-stage stacked structure, achieved a maximum gain of 19 dB, a 3 dB bandwidth from 20 GHz to 26.1 GHz, 1 dB compression point of 12.4 dBm, saturation output power of 16.1 dBm, and a third-order output intercept point of 26 dBm. The chip area is 0.53 mm2. The power amplifier designed with TSMC 90 nm operates in the Ka-band, employing a neutralization with stable capacitor architecture to enhance gain and stability, configured in a four-way stacked structure. The circuit achieved a maximum gain of 12.5 dB, a 3 dB bandwidth from 28.3 GHz to 42.6 GHz, 1 dB compression point of 9.2 dBm, saturation output power of 18 dBm, and a third-order output intercept point of 20 dBm. The chip area is 0.49 mm2.
Finally, Chapter 5 concludes the thesis. |
