超取樣技術之資料回復電路設計與分析; Design and Performance Analysis of Data Recovery Circuits Using Oversampling Technique

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9574

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9574

Title:	超取樣技術之資料回復電路設計與分析;Design and Performance Analysis of Data Recovery Circuits Using Oversampling Technique
Authors:	李政鴻;Zheng-Hong Li
Contributors:	電機工程研究所
Keywords:	雜訊分析;資料回復;超取樣;data recovery;jitter analysis;oversampling
Date:	2003-07-07
Issue Date:	2009-09-22 11:50:52 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	在論文之中，除了針對超取樣電路提出一套完整的雜訊分析流程之外，也將針對奇數倍及偶數倍超取樣的技術做討論。關於應用於雜訊分析所建立的一些評估式子，首先是依據雜訊的種類做分類，再依據實際電路的特性做修正而得。在電路設計方面，則針對奇數倍超取樣倍率改變時，所造成大量的面積浪費的情形做了些討論，遂而提出偶數倍超取樣電路的觀念。此外，為了進一步驗證式子的可信程度，我們也再提出自己的方法來驗證式子的精確程度。這裡驗證工作主要是分兩部分來做，第一部分是產生用來模擬電路雜訊相關的測試資料；第二部分則是由模組產生器產生可合成的Verilog code，再經synopsys中design analyzer軟體來產生閘層級 (gate-level) 的電路。經兩者的結合便可完成電路受雜訊影響的模擬。在模組產生器的設計上，則是將整個超取樣電路透過參數化的過程來使設計具有彈性。使用時則是透過C語言所撰寫的使用者介面，藉由設計者一步步輸入電路的規格來自動產生所適用的Verilog語言。有鑑於整個電路的架構非常規律所以適合以標準庫存元件(standard-cell)的流程完成。也因此使它非常適合當做軟矽智產(Soft Silicon Intellectual Property)。最後經由模組產生器的設計範例將以TSMC 0.25um 1P5M的數位製程予以實現，在未加入preamble的電路時，取樣倍率為3，滑動視窗數目為3，單位滑動視窗中的位元數取8的實驗中，其效率可達2.5Gbps。至於其它不同規格下的模擬結果也已列於本論文第六章之中。 In this thesis, we not only propose a set of jitter analysis but also discuss the technique of the odd and even oversampling ratio. First the estimation formulas are obtained by dividing jitter into two types, random and deterministic jitter. Then we modify them to match the actually characteristics of circuits. In designing circuits, the odd oversampling ratio will cause area waste when the ratio is from one to another such as 3x to 5x. Therefore, we discuss the even oversampling ratio in this thesis. Besides, for verifying the reliability of derived formulas, we also propose a method to check them. Here, we need to do two things before simulation. First thing is to create the transmitted bit pattern with jitter. Second thing is to create synthesizable RTL code from module generator. Then we use design analyzer of synopsys to generate gate level circuits. Finally, the simulation can be done by combining bit pattern with jitter and gate level circuits. In the development of module generator, overall circuits are parameterized for making design more flexible. Besides, our user interface is based on C language. The verilog code will be generated automatically by users, who input the systematic parameters step by step through the user interface. Due to the regular circuit design, it is easy to implement by cell-based design flow. Therefore, it is very suitable to be a soft silicon intellectual property. Finally, a design example generated by the module generator is implemented in a cell-based design method using the TSMC 0.25um 1P5M cell library. Without preamble circuit, the maximum performance of the design, which the oversampling ratio is given 3, sliding windows is given 3 and the number of bits in a sliding window is given 8, can reach 2.5Gbps. The maximum performance of the design can reach 2.5Gbps and the other examples with various specifications are also listed in Chapter 6.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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