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    题名: 於互補式金氧半導體製程之對稱立體式被動元件及壓控震盪器設計;Symmetric 3D Passive Components and VCO Design in CMOS Process
    作者: 陳玟蕙;Wen-Hui Chen
    贡献者: 電機工程研究所
    关键词: 平衡器;變壓器;壓控震盪器;電感;VCO;balun;inductor;transformer
    日期: 2003-07-07
    上传时间: 2009-09-22 11:50:57 (UTC+8)
    出版者: 國立中央大學圖書館
    摘要: 摘要 具有較寬頻帶及較快速資料傳輸速率的無線通訊網路系統,例如:IEEE 802.11a,在最近成為一項吸引人深入研究的領域。隨著互補式金氧半導體製程(CMOS process)的進步,實現低功率,低成本,高整合度的射頻積體電路的可能性大幅提高。本論文以互補式金氧半導體製程之射頻積體電路(CMOS RFIC)為研究目標,研究主題分成兩部分: 第一部份為以互補式金氧半導體之0.18微米製程(CMOS 0.18μm process)製作單晶電感性被動元件之研發,包含電感(inductor),變壓器(transformer)及平衡器(balun)。目前所使用的電感大多為平面式螺旋形架構,耗費較多的面積;且互補式金氧半導體製程之矽基板對被動元件產生的寄生效應造成被動元件之損耗及品質因素降低,因此降低成本及提升元件效能為主要之研究目標。高頻電路設計中需使用到電感性被動元件做許多電路上之運用,例如:匹配網路(matching network),寬頻放大器(wideband amplifier),高頻阻絕(RF chock),電感電容諧振器(LC tank resonator),訊號偶合(signal coupling),相位分離(phase splitting)等等。此類元件在電路中往往佔據相當可觀的面積,因此本論文之研究重點在於研發立體對稱式被動元件架構,有效壓制共模雜訊及減少面積的消耗。對稱立體式電感架構並採用多層金屬並聯的方式,以提升元件之品質因素。同時,本論文中以電位能儲存觀點推導電感之自我共振頻率。經由實際量測結果,對稱立體式在小感值(3nH以下)及高頻段的應用比微型立體式電感有較佳之頻值因素及自我共振頻率,同時,論文中亦提出此對稱立體式電感之應用所在。本論文亦提出一新型對稱立體式變壓器(transformer)架構,以提升元件之耦合效應及在較小面積中實現1:1及1:n之電壓轉換。而所提出之對稱立體式平衡器(balun)在5.25~6GHz頻率範圍之下其增益誤差小於0.8dB,其相角誤差在5.25 GHz為4o。 第二部分為互補式金氧半導體之電感電容壓控振盪器(CMOS LC VCO) 研究。壓控震盪器是射頻電路中重要角色之一,可運用於頻率合成器中,其重要效能參數為相位雜訊、可調震盪頻率範圍、功率消耗。環形震盪器可有較高之可調震盪頻率範圍但相位雜訊表現較差,而電感電容壓控振盪器之可調震盪頻率範圍較窄但相位雜訊表現較佳,且適用於高頻震盪電路。本論文根據相關文獻深入研究電感電容壓控振盪器之相位雜訊模型及改進之方法,整理出設計所需之考量,及設計流程。為避震盪器之震盪訊號受到傳送端之功率放大器之影響,故將震盪器設計在三分之二系統頻段(5.15~5.35GHz)之頻率範圍。因此,以互補式金氧半導體之0.18微米製程(CMOS 0.18μm process)設計3.5GHz四相位電感電容壓控振盪器(Quadrature phase LC VCO),以HP ADS模擬器之模擬結果具有價值參數(figure of merit)為183.5,與最近相關文獻之效能比較結果,此設計具有良好之價值參數,最後藉由實際量測,以驗證模擬及實際結果。 Abstract The Wireless Local Area Networks (WLANs) such as IEEE 802.11a,which have wider bandwidth and faster data communication rate become more attractive in recent investigation. The ongoing down scaling of CMOS gate length and improvement of the CMOS process make it become possible to integrate whole RF transceiver with low power and low cost on a chip using CMOS process. In this thesis,we focus on the CMOS RFICs and the thesis is divided from two part: Part I is the design of the monolithic inductive passive components,including inductor,transformer and balun in CMOS 0.18μm process. Usually,the inductors in recent papers are planar spiral architectures,which occupy larger area. At the same time,the quality factor is decreased due to the series parasitic effect by conductive substrate of the CMOS process. It is the main target to reduce cost and promote the quality factor. The RFICs apply the inductive passive components to matching network,wideband amplifier,RF choke,LC tank resonator,signal coupling and phase splitting,etc. The symmetric 3D passive components can effectively suppress the common mode noise and reduce occupied area. Moreover,the symmetric 3D inductor with improved multi-level shunt has higher quality factor in low frequency and its self-resonant frequency is derived by the concept of voltage distribution and electric energy stored. In experimental result,the proposed symmetric 3D inductor has better quality factor and self-resonant frequency than miniature 3D inductor for smaller inductance (smaller than 3nH) in high frequency applications. At the same time,the symmetric 3D transformers are proposed in this thesis to improve efficiently the signal coupling and approach 1:1 and 1:n voltage transformation in the smaller area. The proposed symmetric 3D balun manifests less than 0.8 dB gain mismatch from 5.25GHz to 6GHz and phase error is about 4o at 5.25 GHz frequency band of interests. Part II is the design of quadrature phase LC VCO,which plays an important role in CMOS RF ICs application. The main considerable parameters are phase noise,tuning range and power consumption. Although the ring oscillator has higher tuning range,its phase noise is bad. On the other hand,the LC VCO has narrow tuning range,but better phase noise performance in high frequency applications. We study the phase noise model and realize the LC VCO design issues and design flow. Note a quadrature VCO based on cross-coupled LC resonators operates at 2/3 of the desired LO frequency f0 (5.15~5.35GHz) to avoid pulling by the power amplifier. Hence,a 3.5GHz quadrature phase LC VCO is designed by ADS simulator in CMOS TSMC018μm process. Finally,the figure of merit (FOM) of this design is equal to 183.5,which is fine compared with the others oscillators in recent papers. Finally,the LC VCO are demonstrated by the measurement.
    显示于类别:[電機工程研究所] 博碩士論文

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