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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9582


    Title: 類神經網路應用於高階功率模型之研究;A Novel High-Level Power Model Using Neural Network
    Authors: 薛文燦;Wen-Tsan Hsieh
    Contributors: 電機工程研究所
    Keywords: 類神經網路;功率預估;高階功率模型;high level power estimation;neural network;power model
    Date: 2003-06-16
    Issue Date: 2009-09-22 11:51:02 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 在預估複雜數位電路的功率消耗時,常用功率模型的方式來預估,這個方法因為在使用上不需要詳細電路的內部資訊,所以在非常高的設計層次中,便能預估到電路的功率消耗。而在這方面目前大多數都是以查表法來實現。然而,當我們利用這種查表法的方式來建立大電路的功率模型時,很有可能為了達到高準確度的目的而將表格大小呈指數比例成長,而且在記錄整個表格的時候,常因為很難去控制輸出轉態機率而造成無法預期的製表時間,這都是我們不願見到的。 在這篇論文中,我們著力研究在利用類神經網路來建立一種嶄新的功率消耗模型,利用類神經網路來學習輸入資訊及相對應功率消耗的值,進而應用在高階功率估測上。我們的類神經功率模組擁有相當低的網路複雜度,不像查表法一樣會與電路大小呈指數性成長,透過特徵萃取處理程序後,我們的模組並不會與電路大小有那麼直接的關係,且因為類神經網路的特性,使得這個簡單的模型還可以擁有很好的準確度。在特徵萃取處理程序中,相較於查表法,我們的是非常簡單且直觀的。更重要的是,這種類神經功率消耗模型不需要內部的電路資訊,不僅保護了智慧財產權,更適合於將來IP盛行的時代。從我們的實驗數據裡可看出,在廣泛的輸入變化範圍內,此功率模型依然保有相當的準確度,足見此模型之效能確實符合需求。 For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. Furthermore, because it is hard to control the distribution of average output transition density, those approaches suffer problems with unpredicted characterization time to fill the lookup tables. In this thesis, we propose a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gate-level description of the circuits, which is very suitable for IP protection. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions.
    Appears in Collections:[電機工程研究所] 博碩士論文

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