English  |  正體中文  |  简体中文  |  Items with full text/Total items : 78852/78852 (100%)
Visitors : 35463336      Online Users : 289
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9584

    Title: MPEG-4 形狀編碼之快速演算法及架構設計;Fast Algorithm and Architecture Design for MPEG-4 Shape Coding
    Authors: 陳嘉彬;Chia-Pin Chen
    Contributors: 電機工程研究所
    Keywords: 形狀編碼;二元移動估計;binary motion estimation;shape coding;MPEG-4
    Date: 2003-06-16
    Issue Date: 2009-09-22 11:51:05 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 本論文提出了一個適用於MPEG-4形狀編碼的快速演算法及其架搆設計。根據二元連續串列的特性,本論文提出一個更為有效的搜尋區域,其搜尋方式符合直觀的搜尋想法。藉由此一快速演算法可大量減少搜尋點數,進而改善MPEG-4形狀編碼的整體運算時間。由模擬結果可得知,在相同的編碼品質下此快速演算法可減少95%以上的搜尋點數。此快速演算法在結合鑽石形的搜尋方法之後,更可減少99%以上的搜尋點數。在影像壓縮率方面,本論文提出一個新的誤差估計法,可得到與絕對誤差和(SAD)相似甚至更佳的壓縮率。我們將此一演算法實現於積體電路上,並完成一個適用於MPEG-4形狀編碼的硬體架構。此形狀編碼器可減少電路運算的時間。此晶片以台積電0.35um 1P4M製程設計,其晶片面積為3.3×3.3平方公釐。而當其操作在21.5MHz時便可完成CIF(352×288)影像格式之即時編碼。 In this thesis, a fast algorithm and architecture design for MPEG-4 shape coding is proposed. Based on the properties of binary shape information, a boundary mask for efficient search positions can be generated. Therefore, a large number of search positions can be skipped. Simulation results show that the proposed algorithm combined with diamond shaped zones takes similar even less bits in the same quality but reduces the number of search positions marvelously in binary motion estimation to 0.8% compared with full search algorithm, which is described in MPEG-4 verification mode. Based on the new algorithm, an architecture design using proposed BME algorithm is developed, and it can reduce the memory access and processing cycles. A prototyping chip is implemented to verify the proposed architecture in 3.3×3.3mm2 die area, and the clock frequency is 40MHz. For real-time applications, the proposed encoder can deal with CIF(352×288) sequence when operating at 21.5 MHz.
    Appears in Collections:[電機工程研究所] 博碩士論文

    Files in This Item:

    File SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明