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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/9586


    題名: 一個1.8V CMOS OC-192傳送器;A 1.8V CMOS OC-192 transmiiter
    作者: 劉嘉俊;Chia-Chun Liu
    貢獻者: 電機工程研究所
    關鍵詞: 傳送器;鎖相迴路;延遲鎖相迴路;光纖通訊;PLL;DLL;transmitter;OC-192
    日期: 2003-07-07
    上傳時間: 2009-09-22 11:51:07 (UTC+8)
    出版者: 國立中央大學圖書館
    摘要: 時至今日,高品質的商業化之10GHz之IC電路所使用之元件多為bipolar及3-5族元件,而使用CMOS 製程來實現此電路有其存在的困難度及缺點,一方面其 ft 較bipolar 及III-V 族差 而1/f noise 相對於bipolar也較差 而 在若無使用triple well ,substrate noise 也會因為其substrate之良導性而到處流動,那當然使用CMOS來實現對於系統整合上有其優勢 而對於慢速的邏輯電路上使用CMOS來實現,有較低的功率消耗. 以晶片包裝上來說, CMOS之封裝發展的較成熟及廉價.以製程來說 CMOS最大的優勢是便宜, 極為便宜而因為使用的極為廣泛,故 有較佳較準確之model及寄生可以使用 而在現今的無線通訊系統中,鎖相迴路( PLL )是一個產生本地訊號源的重要架構,而鎖相迴路所消耗的功率常常占了系統很大的一部份。而其中鎖相迴路中的電壓控制震盪器及除頻電路,在高頻下之功率消耗大為可觀,為了減少功率消耗,我們將朝向設計一低功率且可工作於高頻之頻率合成器而努力,而現今相關研究發展中,高頻電壓控制震盪器之輸出多為互為反向之兩相位,此種做法對於接收端之解調變的設計上有些許不便,而對於光纖系統之接收端,我們為了要使得資料回復,在電路上也需要多相位的性號產生器。因此在此我們對於性號輸出上採用同步四相位輸出之設計。 在回授路徑上,由於目前除頻電路的設計上多採用D flip-flop的方法來設計,而此種設計上,一方面極為浪費功率,尤其是在設計一可操作於高頻之D flip-flop,在此我們為使電路能夠在較高的頻率上操作故使用Injection locked架構來做為除頻,而日前國外所提出之Injection locked架構確實較Regenerative frequency dividers及Parametric frequency dividers適用,且其消耗的功率遠小於一般除頻電路。 此外,為了穩定ILFD的直流偏壓,我們加入了一個DLL來供給ILFD所需要之直流偏壓,其中的Delay cell均為ILFD的基本單元,以減少mismatch。另外,在實踐多工器( MUX )方面,由於我們的除頻器能夠對於10GHz的頻率,做出除八,然後八個均勻相位的訊號,因此,我們運用此特性,來實踐出一個16對一的多工器。 Most of component used in high quality commercial 10GHz IC circuit product is fabricated by bipolar of III-V A group till today and it has some difficulty and disadvantage to implement the circuit by CMOS. On the one hand, CMOS has lower ft than bipolar and III-V A group and on the other hand, the 1/f noise is more poor than bipolar. If there is not triple well can be used, substrate noise will flow in substrate. So there is some advantage to integrate system chips by CMOS. There is lower power consumption in low speed logic circuit implemented by CMOS. For chip package, it is cheaper and the technique is more mature in CMOS package. For chip fabrication, the bigger advantage for CMOS fabrication is cheap and has been used extensively, so it has better and more precise model can be use. In today’s optical communication system, phase locked loop ( PLL ) is an important building block to generate a local oscillation ( L.O. ) signal and PLL often consume a major part in total power. The voltage controlled oscillator ( VCO ) and divider circuit in PLL consume a huge power in high operating frequency. In order to reduce the power consumption inspired the motivation of this thesis. In today’s research, most high frequency VCO outputs are IQ phase. This structure is not so good for de-modulation in receiver. In order to recover the data in receiver for optical systems, the synchronous quardture phase output VCO is adopted. In feedback path, many divider circuit structure are D flip-flop based. It consumes huge power and can’t operate at high frequency, so the injection locked frequency divider is adopted here. The injection locked frequency divider which had been proposed can really consume much less power and operate at higher frequency than Regenerative frequency dividers and Parametric frequency dividers. Otherwise, in order to give a stable DC voltage to ILFD to pull the free run frequency near the locking range, a DLL is added to give the DC voltage need by ILFD. The delay cell is the basic cell used in ILFD to reduce mismatch. Because the ILFD can produce eight well-distributed phase and divided eight signals, so in implement multiplexer ( MUX ) the character can be used to reduce the extension of jitter. The whole transmitter is fabricated in TSMC 0.18?m CMOS 1p6m process, the whole chip size is 1.6 X 1.05 mm2, total power consumption is 288.63mW.
    顯示於類別:[電機工程研究所] 博碩士論文

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