在這一個論文中，我們設計了兩個鎖相迴路，第一個是使用傳統電荷充放器(Charge pump)以及相位頻率偵測器(Phase frequency detector)為基本架構的鎖相迴路，操作在1.25GHz並有多相位的輸出。第二個鎖相迴路使用雙迴路架構，並使用兩個控制訊號來控制一個粗調/微調壓控震盪器，這個雙迴路的架構可以降低控制電壓雜訊所造成的時脈抖動，當雙迴路鎖相迴路在獲取狀態時，兩個迴路同時工作以達成鎖定，當鎖相迴路達到穩定時，粗調部分的迴路將會停止工作並且讓微調部分的迴路維持鎖定狀態，因為微調部分的迴路具有較小的壓控震盪器(Voltage controlled oscillator)增益，所以由控制電壓雜訊所產生的時脈抖動將會縮小。兩個鎖相迴路都可以應用在高速傳輸介面(High speed serial link)的傳送端。由模擬的結果得到第一個鎖相迴路具有6ps的時脈抖動，而第二個鎖相迴路具有3.8ps的時脈抖動。兩個鎖相迴路都可以使用台機電0.18 1P6M製程以及操作在1.8伏特。 In this thesis we design two phase-locked loops. The first phase-locked loop is a traditional one which utilize charge-pump and phase-frequency detector as the basic structure. It operates at 1.25GHz with multi-phase outputs. The second phase-locked loop is a dual loop phase-locked loop using the coarse/fine tune voltage controlled oscillator and two control paths. The dual loop structure can suppress the jitter induced by the control voltage noise. When the dual loop phase-locked loop is in acquisition state, both loops are active to achieve lock. After the phase-locked loop is in the steady state, the coarse tune loop stops working and leaves the fine tune loop to maintain the lock. Because the fine tune loop has the control path with smaller VCO gain, the jitter induced by the control voltage noise will be suppressed. Both phase-locked loops can be applied in the high speed serial link transmitter. The simulation results shows that the first phase-locked loop has 6ps peak to peak jitter and the second has 3.8ps peak to peak jitter. Both phase-locked loops can be fabricated in TSMC 0.18μm 1P4M technology with 1.8V power supply voltage.
