一個低功率的MPEG Layer III 解碼器架構設計; A Low Power Design for MPEG-1 Layer III

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/9594

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题名:	一個低功率的MPEG Layer III 解碼器架構設計;A Low Power Design for MPEG-1 Layer III
作者:	陳玟丞;Wen-Cheng Chen
贡献者:	電機工程研究所
关键词:	低功率;超大型積體電路設計;MP3;mpeg;mp3;layer III;low power;csd;huffman;vlsi
日期:	2003-07-03
上传时间:	2009-09-22 11:51:18 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	隨著多媒體技術的進步，許多高品質的音訊信號已經深入家庭，但由於網路頻寬的限制，所以必須對這些高品質的音訊信號做有效率的壓縮。MPEG這個國際標準組織便提出了一些標準壓縮演算法，包括MPEG-1、MPEG-2、MPEG-4等。在這份論文當中，我們就針對較受大眾歡迎的MPEG-1 Layer III音訊解碼器的流程，提出一個低功率消耗及高效能的硬體架構。由於在SOC的時代中，功率消耗將是個很大的課題，所以我們也針對我們的設計，提出一些低功率消耗設計的考量。在這設計中我們針對低功率消耗的考量包括有：提出一個低功率消耗的Huffman Decoding架構，利用CSD的方法去替代我們架構中的乘法器，以及利用演算法來替代在反量化中查表時所需的記憶體大小。最後我們使用avant! 0.25um cell，以cell-based的方式來完成整個MPEG-1 Layer III 解碼器。面積為3.1x3.1 mm2, 操作頻率為20MHz。在符合即時處理的應用之下，本晶片只要在工作頻率為5MHz的時候既可達到此要求，並且所消耗的功率約84mW。 With the advance of multimedia technology, most high-quality audio signals are already been used popular in our lives. , due to the limitation of the bandwidth in network communication, the sufficient compress process must be necessary for these high-quality audio signals. The international organization for standard was to initiate the development of common standard for compress digital audio signal, including MPEG-1, MPEG-2, and MPEG-4…et. In the SOC design today, the designers may integrate many well-designed circuit blocks called intellectual properties (IPs) and some self-designed circuit blocks to build up the complex system in a short time. While designing such complex systems, power consumption is also a very important design issue. In this thesis, we will target at the most popular MPEG-1 Layer III audio decoder flow to propose a novel architecture with low power consumption and high efficient hardware architecture. In the power consumption issue we have propose a several improvement points including: low power Huffman Decoding architecture, using CSD approach to instead of the multiplier in our architecture, and reducing the memory size of lookup table. The proposed decoder system have been designed and implemented using VLSI cell-based approach and die size is 3.1x3.1 mm2 and operation speed is 20MHz. For the real-time application purpose, our design can easily achieve this purpose by operating at 5MHz and the average power consumption is approximate 84mW.
显示于类别:	[電機工程研究所] 博碩士論文

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