用於具延遲/迴旋處理器之籬柵碼的超籬柵解碼; Super-Trellis Decoding for Trellis Codes with A Delay/Convolutional Processor

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9641

Title:	用於具延遲/迴旋處理器之籬柵碼的超籬柵解碼;Super-Trellis Decoding for Trellis Codes with A Delay/Convolutional Processor
Authors:	盧俊宇;Chun-Yu Lu
Contributors:	電機工程研究所
Keywords:	延遲處理器;籬柵碼;時空碼;硬式決定重複性解碼;delay processor;trellis code;space-time codes
Date:	2003-06-17
Issue Date:	2009-09-22 11:52:26 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文提出對具延遲/迴旋處理器之籬柵碼的解碼演算法，此解碼演算法是利用由原始籬柵擴充而成的超級籬柵。此解碼方式可以改善大部分由原始籬柵解碼所造成的錯誤係數。此外，我們運用硬式決定重複性解碼 (hard-decision iterative decoding) 來改善其錯誤率效能。接著在半平穩衰退通道下，我們將具延遲/迴旋處理器之籬柵碼結合時空區塊碼而形成時空籬柵碼，基於此時空籬柵碼之超籬柵解碼演算法也在此討論。基於相同複雜度下，使用超籬柵解碼會比使用原始籬柵解碼得到較好的錯誤率效能。 In this thesis, we propose decoding algorithms for trellis codes with a delay/convolutional processor, these decoding algorithms are based on a super trellis which is expanded from the original trellis. The proposed decoding can avoid most of the increased error coefficients caused by the decoding with the original trellis. In addition, hard-decision iterative decoding is used to improve the error performance. Moreover, the trellis code with a delay/convolutional processor is combined with the space-time block code to form a space-time trellis code for the quasi-static flat fading channel. The error performances of the decoding algorithms based on a super trellis for this space-time trellis code are investigated. Based on the same complexity, the error performances of the decoding with a super trellis are better than those of the decoding with the original trellis.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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