近年來，半導體製程技術快速的發展。在半導體產業裡，元件特性的模擬經常被使用來降低製造的成本與時間。因此開發半導體元件模擬器就變成相當重要的任務。然而在二維或三維元件的數值模擬分析裡，是需要消耗大量的記憶體空間和電腦計算時間。因此在本論文中，我們提出了元件分割法(device partition method)、小電阻連線法(small-resistance coupling)及準三維的元件模擬技術來改善我們現有的元件與電路混階模擬器的效率。在元件分割法的研究方面，我們已經展示出元件模擬所需的記憶體空間會隨著元件分割數目的增加而降低。在電腦計算時間的改善方面，我們在三維的元件模擬裡也觀察到電腦計算時間會隨著元件分割數目的增加而降低。另外，在元件與電路混階模擬研究方面，我們已經提出了小電阻連線法來改善過去無法以帶狀形矩陣(band matrix)解法器來探討外部連線較複雜的元件與電路模擬。在本論文裡，我們也使用小電阻連線法來探討負微分電阻、石英晶體及環狀型振盪器等電路。在準三維的元件模擬研究方面，因為主要載子的準費米能階(quasi-Fermi level)幾乎為水平，所以外部的電壓源可以直接加在主要載子的電路上且可得到一近似以傳統三維元件模擬器計算的解。在應用方面，我們也以此準三維元件模擬的技術來探討body-tied結構的SOI MOSFET和動態式臨界電壓的(dynamic threshold voltage) MOSFET。最後，我們分別以垂直積分法和水平積分法的等效電路模型來探討非理想的金氧半電容的平帶電壓(flat-band voltage)。 In the recent years, the semiconductor manufacturing technology proceeded at a very rapid pace. The simulation of device’s characteristic is always used to reduce the manufacturing cost and time in the semiconductor industry. Therefore, it is a very important task to develop the device simulation. However, it requires a considerably huge amount of memory size and calculation time in 2-D or 3-D device simulation. Therefore, we propose the device partition method (DPM), small-resistance coupling (SRC) method, and quasi-3D technique to improve our mixed-level device and circuit simulator in this dissertation. In DPM, we have demonstrated that the lower consumption of memory accompanies the larger part number of DPM in 2-D or 3-D device simulation. Besides, we have also demonstrated that the calculation time decreases as the part number of DPM increases in 3-D device simulation. Furthermore, we have proposed SRC method to improve the limit on the discussion of the complicated mixed-level device and circuit simulation using the band matrix solver. In this dissertation, we also use SRC method to study the negative-differential-resistance oscillator, crystal oscillator, and CMOS ring oscillator circuits. In the quasi-3D device simulation, because the quasi-Fermi level of majority carrier is nearly constant, the voltage source can be connected to the majority carrier circuit. Therefore, we can obtain the solution that is close to the conventional 3-D device simulator. In the application of quasi 3-D device simulation, we also use the quasi-3D technique to study the body-tied SOI MOSFET and dynamic threshold voltage MOSFET (DTMOS). Finally, we use the equivalent circuit models for the vertical and horizontal integrations to study the flat-band voltage of non-ideal MOS-C.
