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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9678

    Title: 應用於無線區域網路5.8GHz 射頻接收電路之研製;Implementation of 5.8 GHz RF Receiver Circuits for WLAN Applications
    Authors: 陳政平;Jenq-Pyng Chen
    Contributors: 電機工程研究所
    Keywords: 射頻;低雜訊放大器;混頻器;二次諧波;收發開關電路;鏡像抑制混頻器;Image Rejection Mixer;TR Switch;sub_harmonic;MIXER;LNA;CMOS;RF
    Date: 2004-07-07
    Issue Date: 2009-09-22 11:53:22 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 摘要 本論文主題在於使用標準金屬氧化半導體製程(tsmc 0.18μm 1P6M CMOS)來研製應用於 802.11a WLAN 之5GHz U-NII 頻帶5.725~5.825GHz 接收電路CMOS RFIC。實現在5.8GHz的低雜訊放大器、收發切換開關電路、鏡像抑制混頻器、直接降頻混頻器。 第一部份為5.8GHz CMOS 使用主動偏壓電路的低雜訊放大器,量測結果如下:增益約14dB、雜訊指數為4.3 dB、IIP3/OIP3 截斷點約為5dBm / 20dBm、P1dB 增益壓縮點為-11dBm。第二部份為5.8 GHz CMOS 收發切換開關電路,分別為指叉數(number of finger)為16 個與指叉數為128 個,指叉數為16 個的量測結果如下:插入損耗為2.39 dB、隔離度為35.75dB、P1dB增益壓縮點為18 dBm,另一個指叉數為128 個的量測結果如下:插入損耗為1.75 dB、隔離度為27.4dB、P1dB 增益壓縮點為17 dBm。第三部份為5.8GHz CMOS 鏡像抑制混頻器,量測結 果如下:轉換損耗為-4 dB、P1dB 增益壓縮點為-14 dBm、雜訊指數為23dB、隔離度均為40dB以上、IIP3/ OIP3截斷點約為 0dBm / -5.1dBm、鏡像抑制為18dB 左右。第四部份5.8 GHz CMOS降頻諧波混頻器,可分為兩種架構,第一種架構為轉換損耗為-2 dB、P1dB 增益壓縮點為-6dBm、隔離度均為30dB 以上、IIP3/OIP3 截斷點約為-2.5dBm / -4dBm;第二種架構為轉換 損耗為-5.2 dB、P1dB 增益壓縮點為-6dBm、隔離度均為30dB 以上、IIP3/OIP3 截斷點約為3dBm/-5dBm 在tsmc 0.18μm 1P6M CMOS 製程的RF model 已趨於準確以及穩定下,只要加以小心的設計及佈局,均可以得到不錯的5.8GHz 的電路特性。以及再加入精準的偏壓電路,則可成功將5.8GHz CMOS 晶片做更進一步的整合。 Abstract The work use tsmc 0.18µm 1P6M CMOS technology to develop 5GHz U-NII band 5.725GHz~5.825GHz CMOS RFICs for the 802.11a WLAN receiver. The designed 5GHz RFICs include the low noise amplifier, T/R switch, image rejection mixer, sub-harmonic mixer.The first part of the thesis is the design of 5.8GHz low noise amplifier. The performances are obtained as the gain of 10.5 dB, noise figure of 4.13 dB, input and output third order intercept point of 6dBm /14.5dBm, input 1 dB compression point of –9dBm. The second part of the thesis is a 5.8GHz T/R switch. The following performances were measured as the insertion loss of 2.33dB, isolation of 35.75dB, input 1 dB compression point of 18dBm in 16-finger device. The performances are shown as insertion loss of 1.75dB, isolation of27.4dB, input 1 dB compression point of 17dBm in 128-finger design. The third part of the thesis is of 5.8GHz image rejection mixer. The measured results are the conversion loss of 4.2 dB, input 1 dB compression point of -14dBm, noise figure of 23dB, isolation is greater than 30 dB, input and output third intercept point of 0dBm /-5.1dBm, and image reject ratio is 19dB. The fourth part of the thesis is a 5.8GHz subharmonic Mixer. The measurement results are achieved as follow. The conversion loss is 1.15dB, input power at the 1dB gain compression point is -6dBm, signal isolation is greater than 30dB, and input third intercept point is -2.5 dBm/-4dBm. The other Gilbert cell mixer was designed for comparison. It obtains the conversion loss of 5.15dB, input power at the 1dB gain compression point is -6dBm, signal isolation is greater than 30dB, and input third intercept point is 3dBm/0.5dBm. Since the accuracy of tsmc 0.18 µm CMOS RF model, the designed RFICs show very good agreements between the simulations and measurements under careful design and layout procedures. The basic cell circuits for 5 GHz band receiver including LNA, switch, and mixer are successfully developed in this thesis. The future work will integrate these circuits to be a high level receiver.
    Appears in Collections:[電機工程研究所] 博碩士論文

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