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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9681

    Title: 應用於矽製程的去嵌入技術、電感及接觸墊之研究;The Study on the Application of De-embedding Techniques, Inductors and Pads in Silicon Process
    Authors: 楊渝澤;Yu-Ze Yang
    Contributors: 電機工程研究所
    Keywords: 去嵌入;接觸墊;電感;Inductors;De-embedding;PADs
    Date: 2004-10-08
    Issue Date: 2009-09-22 11:53:27 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 摘要 本論文主題在於以現有的矽基板製程(CMOS、SiGe)來對於去嵌入技術、螺旋型電感以及接觸墊的寄生效應作一探討。冀望於此探討中,得到最佳的去嵌入機制,以獲得最準確之元件量測結果。同時在電感方面,能夠擁有最佳的品質因數和自振頻率的電感。最後,希望能得到寄生效應最為微弱,卻又能不造成量測困擾的接觸墊。 第一部份是介紹去嵌入機制,將目前較常為人所用的去嵌入機制分別敘述,並以量測結果作一比較,從中找出一最方便、最精準的方式,最後得到的結果,是以接地屏蔽層去嵌入機制所得到的數據最佳。第二部分是探討目前所使用的螺旋型電感,從最基本的電感原理著手,再延伸至目前於矽製程上所使用的螺旋型電感。包括電感的寄生效應、元件模型、品質因數及其改善方法。最後,利用不同的規格的電感做量測,並比較電感值和品質因數的差異。其結果是利用矽鍺製程中的格狀深溝槽屏蔽的方式,可獲得最佳的品質因數,且仍能維持電感原有的特性。第三部分討論的是接觸墊的寄生效應及其改進方法。文中利用防護圈的方式,可有效的降低電阻性的損耗,使得基板效應降低。 由於在矽製程上射頻電路的實現,使得設計者對於製程的要求,無論是製程特性,或是元件模型的準確度都越來越高。然而,矽製程仍然有其限制存在。因此,如何利用現有的製程,在不增加製作成本的前提下,使所設計的電路發揮最大效能,仍是一個需要努力的目標。 Abstract The purpose of this thesis studies on the de-embedded techniques applied in silicon base processes, such as CMOS and Silicon-Germanium technologies, the de-embedding techniques, parasitic effects, spiral inductors, and PADs will be discussed in detail. The spiral inductor designs are investigated with different shielding techniques. The quality factor Q and self-resonant frequency are the figure of merit of these inductor designs. The inductor with mesh deep trench shielding achieved the best quality factor and highest self resonant frequency. Finally, a PAD model is investigated and the equivalent circuit model is presented up to 20 GHz. The first part in this thesis is to introduce the de-embedding structure. Several de-embedding methods are introduced and given some meaningful comparisons. The completed de-embedding techniques and parameter extraction procedures are presented using straightforward mathematic calculations. The ground-shield de-embedding structure obtains the best results among the others methods. A small signal device model of CMOS is demonstrated by using these techniques. The second part is the study of spiral inductors. The basic inductance principle is first introduced. Modern planar spiral inductor used on the silicon-based technology is then studied including its parasitic effects, device model, quality factor and the method of improving. Finally, compare the difference with inductance value and quality factor by the measurement of inductors with different specifications. The inductor with mesh deep trench shield in silicon germanium obtains the best quality factor. The third part discussion is the parasitic effect of the PAD and improving method of PAD is proposed. Using the guard ring can reduce the resistance loss and the substrate effects effectively. Since the implementation of radio frequency circuits on silicon plays very important role in the recent novel emerging applications, the request for precise processes, accuracy device models get more and more important. However, the silicon process still has existence of limiting. It’s a goal to use existing process under the major premise of maintaining the cost of manufacture which makes the circuit design accomplish the greatest efficiency.
    Appears in Collections:[電機工程研究所] 博碩士論文

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