直到現在，邏輯模擬器依然是最受歡迎的驗證工具。雖然它們可以在驗證過程中提供使用者對於被驗證之電路有完全的控制性與觀察性，但是當有大量的輸入測試訊號時，整個模擬速度將會太慢。此時若使用像可程式化邏輯陣列這樣的仿真工具，將可得到更高的模擬速度。然而在速度獲得提升之後，另外一個問題也同時產生，那就是可程式化邏輯陣列所能提供之觀察度實在太低，如此將導致驗證上的困難變高。 所以，在這篇論文中，我們提出另外一種方法來改善上述的一些短處。運用此方法，我們會記錄可程式化邏輯陣列內部的行為，之後在邏輯模擬器上跑出我們所想要之區段的波形。因為大部份的過程花費都是在可程式化邏輯陣列上，所以使用者仍可得到高速的好處。而且，對電路之完全觀察度以及相對於硬體之較佳驗證環境則可以在軟體的邏輯模擬器上獲得。 透過實驗數據的說明，可以看到使用我們所提之方法的效率。 Until now, logic simulators are still the most popular verification tools. Although they can provide full controllability and observability during the verification process, its running speed is too slow for large amounts of input patterns. Using hardware emulation such as FPGA (field programmable gate array) can have higher simulation speed. However, it is very hard to debug using this approach due to poor visibility in FPGAs. Therefore, in this thesis, we propose another approach to “record” the internal behaviors of an FPGA and “replay” the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in the FPGA. Moreover, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.
