抗雜訊之邏輯元件設計與實現; Design and Implementation of Low Jitter Logic Blocks

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Title:	抗雜訊之邏輯元件設計與實現;Design and Implementation of Low Jitter Logic Blocks
Authors:	蔡昌孝;Chang-Hsiao Tsai
Contributors:	電機工程研究所
Keywords:	時間抖動;jitter
Date:	2004-07-07
Issue Date:	2009-09-22 11:53:48 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	在本篇論文，我首先分析數位電路的時間抖動特性，且將抖動的成因分成四類：包含了電源訊號的抖動，基板的雜訊，時脈的不穩定性，還有輸入資料相關聯性的抖動。我們在經常使用的資料暫存器與多工器中提出了一種較少時間抖動的架構，再加上調整尺寸與佈局方式可以降低時間抖動。一般我們量測到在輸出波形的時間抖動的量值都是由數種時間抖動的成因組成。針對資料暫存器，我們提出了一個可以累積除了時脈不穩定性因素外的所有成因造成的時間抖動量值之電路架構，由此電路我們可以在輸出波形處，量測到大部分是由除了時脈不穩定性因素外的所有成因造成的時間抖動量值。我們使用台積電0.18微米製程並針對抗雜訊加以設計模擬的結果，對於資料暫存器峰對峰的時間抖動量值只有1.17兆秒，對於多工器峰對峰的時間抖動量值只有0.04兆秒。 In the thesis, we first analyze the jitter of digital circuits. We divide the jitter source into four categories: vdd / gnd bounce jitter, substrate noise jitter, data dependent jitter, and clock jitter. For the frequently used flip-flop and MUX, we propose an architecture that has the least jitter. Also, sizing and layout techniques are used to decrease the jitter. In general, the measurement results of output waveform jitter consists of several kinds of jitter. For the D-flip-flop we propose an architecture that could accumulate the output jitter, except for clock jitter so that the output waveform mainly consist of output jitter, except for clock jitter. Design results show that the low-jitter architecture can achieve only 1.17ps and 0.04ps (peak-peak) for D-flip-flop and MUX respectively, using TSMC 0.18um CMOS technology.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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