應用於正交分頻多工通訊系統及ARM平台之快速傅立葉轉換器與矽智財產生器設計; An FFT Soft IP Generator for OFDM Communication Systems and ARM Base

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Title:	應用於正交分頻多工通訊系統及ARM平台之快速傅立葉轉換器與矽智財產生器設計;An FFT Soft IP Generator for OFDM Communication Systems and ARM Base
Authors:	彭振淇;Chen-Chi Peng
Contributors:	電機工程研究所
Keywords:	矽智產;傅立葉運算;正交分頻多工;OFDM;IP;FFT;IFFT
Date:	2004-10-19
Issue Date:	2009-09-22 11:53:50 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本次設計主要提出一個適用於多種以正交分頻多工OFDM ( Orthogonal Frequency Division Multiplex) 為架構之通訊系統的設計技術與方法,由於OFDM是利用IFFT/FFT之原理來做調變/解調,利用IFFT/FFT的方式完成的OFDM除了在製作上變的更容易之外,他還有降低通訊傳輸當中ISI與ICI等效應. 為了有效率的重覆使用我們所設計的快速傅立葉運算架構,我們分析快速傅立葉運算之中可提供改變的參數,並且找出其中共通性的規則及模組化架構,發展出一個可以自動化產生Verilog 的 Soft IP 產生器.這個IP產生器以GUI視窗作為使用者介面,而核心為完全可合成(Synthesizable)的Verilog模組,對於不同的用途,此一IP產生器能夠根據使用者輸入的參數自動產生相對應的Soft IP,Test Pattern 及模擬用的Script 檔案,如此一來更可以廣泛的使用在各種層面上.所得到的synthesizable Verilog code除了可以直接加進使用者本身的設計（Verilog code）,也可以轉成layout後再merge,或者可以獨立開來下載到FPGA後再作系統的整合.我們的IP Generator 也提供了一個on-chip-bus的溝通介面. In this thesis, we design an automatic generation environment for hardware accelerator of Fast Fourier Transform (FFT) and inverse Fast Fourier Transform (IFFT) with various parameters. The target application is the FFT/IFFT core from 8 to 8192 points for OFDM systems. With different input parameters and constrains, our FFT/IFFT Soft IP generator can automatically generate a complete design results including the synthesizable Verilog HDL code, test bench, and synthesis scripts files. We also produce the on-chip-bus interface circuit compliant with the AMBA protocol and associated device driver so that the generated IP is ready for system-on-chip (SOC) integration. Therefore, not only reducing the time-to-market development cost, the proposed design can provide a reuse and programmable IP core which is suitable for the SoC application.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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