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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9711

    Title: 應用於高速鏈結之全數位時脈與資料回復電路架構;All Digital Clock and Data Recovery Circuit Architecture for High Speed Serial Link
    Authors: 李建錫;Chien-Hsi Lee
    Contributors: 電機工程研究所
    Keywords: 時脈與資料回復電路;高速序列鏈結;clock and data recovery;high speed serial link
    Date: 2004-07-07
    Issue Date: 2009-09-22 11:54:12 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 近年來,隨著多媒體應用的蓬勃發展與製程技術不斷地演進,晶片上的處理時脈頻率已超過3GHz。而資料處理量越來越多的狀況下,系統的表現良好與否就會反應在傳輸的問題之上。再者,網路的各種應用目前已經需要相當巨大的資料傳輸率,面對如此高傳輸量的需求,勢必在有限的通道(Channel)傳輸越來越多的資料量已經變成一個不可避免的趨勢。 由於傳輸過程中雜訊對信號所構成的影響隨著傳輸速率的增高而日益嚴重。通道與通道間的交互影響(Cross Talk)或著電磁發散(EMI)、阻抗的不匹配造成信號反射、通道本身會對訊號產生程度上的衰減,另外非理想的傳輸端信號會有頻率與相位上的飄移…等等,種種因素將使得如何達到高速而正確的傳輸,並降低有限通道頻寬與外來雜訊的影響,進而接收到正確的資料成為一個難以克服的問題。於是乎,應用於高速鏈結的資料回復技術在這些傳輸的問題之中勢必伴演著極為重要的角色。 在第一章中,我們會介紹接收機在整個高速傳輸裡面所扮演的角色,並比較近年來工業界較為熱門的一些輸入/輸出介面的標準。 在第二章中,我們會介紹在一些由雜訊所引起的非理想現象。而傳統上的一些資料回復技術也將分門別類地一一介紹。 在第三章中,我們首先透過機率的理論來預測誤碼率。接著,利用C語言來建立兩種不同的資料回復方法。透過系統層次的模擬並分析所得到的結果,我們便可決定合適的系統參數。在此,我們做了許多參數交互變動的模擬,並依此決定出最合適的系統參數。 在第四章與第五章裡,我們將第三章中的兩個模型分別轉換到電路的實體層,除了電路架構外,我們也會詳述設計考量與模擬的結果。 最後,在第六章裡將把本篇論文做總結。 In recent years, communication networks can provide high bit-rate transport over a shared medium with a serial line or link, such as passive optical networks, cable television networks (fiber, coaxial or hybrid), digital television, and wireless networks. These shared-medium networks typically use time, frequency or code division multiplexing to transport data signals from a central terminal to several remote customer terminals and from the customer terminals to the central terminal. Among them, time division multiple access (TDMA) is characterized by non-continuous or burst mode data transmission. Traditionally, clock and data recovery (CDR) methodologies are provided for communications systems receiving continuous data streams that have enriched spectra at the sampling frequency. CDR is a useful functionality in high-speed transceivers. The received data are asynchronous and noisy, thus requiring that a clock be extracted for allowing synchronous operations. The data also need to be retimed so that jitter accumulated during data transmission can be removed. The over-sampling techniques and phase picking algorithm are applied in this work. In addition, we try to give more creativity in the changing the architectures. In other phase picking methods, multiple bits are sampled in parallel to form a sliding window and have an average effect on the phase detection. The size of such a window defines how much information is extracted from the input data. It is a fixed design parameter. The bigger window size is suitable for the high frequency noise environment; the smaller size window has a better acquisition speed. In this thesis, two all digital approaches of timing recovery techniques have been proposed. After the system level simulations of the two proposed methods, we can specify the system parameters and map to the real blocks in the circuit level. Both of them have been realized with tsmc 0.18μm 1P6M CMOS technology.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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