隨著網際網路和串列傳輸介面的蓬勃發展，有線串列式傳輸系統如光通訊收發系統、PCI-Express、serial-ATA、…等。串列式傳輸可減少傳輸線的數目，而使得所需要的面積、成本變少，更可減少了EMI效應。故高速的串列傳輸介面已逐漸取代平常使用之纜線及匯流排線，且隨著多媒體資訊應用日益廣泛，不論是應用在網際網路上資料傳輸之光通訊收發系統、電腦內的高速PCI-Express資料匯流排或是應用在儲存元件內的serial-ATA資料傳輸介面，使用者對資料傳輸頻寬的須求也日益增加，故在研究高效能、高傳輸速率、高整合性、低功率消耗及低成本之串列傳輸介面方面刻不容緩。 本論文之設計主要針對光纖通訊系統中的SONET OC-192規格中的串列式發射器為設計藍圖，在此發射器裡包含一個時脈倍頻電路及一個可將十六筆622.08Mbps的平行式資料轉成一筆9.9533Gbps串列式資料的串列多工器。時脈倍頻電路其功能依據SONET OC-192所確立之標準，由一622.08MHz本地振盪源經頻率合成產生八個均勻相位的1.24416GHz之輸出參考時脈信號的鎖相迴路電路。資料串列多工器利用時脈倍頻電路所產生的多相位時脈的時間相互關係，採用兩級式串列架構將十六筆622.08Mbps的平行式資料轉成一筆9.9533Gbps串列式資料，以逹到低功率消耗及低成本的設計。此電路採用TSMC 0.18μm CMOS製程技術，操作電壓為1.8V之下，總功率消耗為435毫瓦。 在收發系統中，收發器電路的傳輸錯誤率通常為其收發器效能的指標，由於現今收發系統發展快速，傳輸速率日益增高，在高速測試儀器也就水漲船高，測試成本也就高不可攀，然而內建試收發系統測試電路只須在晶片中增加一點面積即可立即測試出此晶片的效能，也為此收發系統大大的降低其量測成本。其中利用一偽亂碼產生器產生測試用的測試亂碼，再利用接收端本地的另一組偽亂碼產生器配合許多判斷及控制電路產生發射端相同的測試亂碼以利做傳輸錯誤率的判斷，再利用計數器統計結果。此電路採用TSMC 0.18μm CMOS製程技術設計，操作電壓為1.8V之下，最高可量測40Gbps 16對1的串列/解串列收發機，其可量測錯誤率為10-5~10-14的解析度，最高速時平均功率消耗為36毫瓦。 The rapidly-growing volumes of data in telecommunication network have rekindled interest in high speed optical and electronic device and system. The serial-link transceiver system such as optical transceiver system, PCI-Express, serial-ATA、etc.. Because serial-link transmission is less transmission line, the effect of EMI, chip cost and area will be reduced. The cable and Bus will be replace by high speed serial-link transceiver. Wherever high speed serial-link transceiver apply to optical transceiver system in internet, high speed PCI-Express data Bus in computer and serial-ATA in storage component, the bandwidth requirement is increase day by day. Therefore, it is important to research high performance, high speed, high integration, low power consumption, and low cost serial-link transceiver side. The subject of this thesis is the design for optical communication system which conform SONET OC-192 specification. The transmitter comprises a clock multiply unit(CMU) and a data serializer which transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data. The function of clock multiply unit (CMU) is designed for SONET OC-192. Its function is to synthesize a 8 phase 1.24416GHz output signal from a 622.08MHz reference source. The data serailizer is adopted two stage architecture to transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data by multi-phase relation to achieve a low power consumption and low cost design. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. Total power consumption is 435mW. The bit error rate (BER) is an index of transceiver system in general. Because the data rate of the transceiver system is increased quickly, the high speed test equipment is very expensive. Built-in test only need to add a small area in chip to test the chip performance. Therefore, the cost of testing will cost down vastly. In this design, a pseudo random bit sequence (PRBS) generator generates a test code in to device under test (DUT). And then, tester receives data form DUT to generate corresponding PRBS code to test bit error rate by decision block and control unit. Finally, the counter counts the number of error. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. The highest operation of the tester is suit for 16:1 40Gbps serial-link transceiver. The resolution of the test is 10-5~10-14. Total power consumption is 36mW in highest speed operation.
