高速前端光接收器之單石積體化技術; Monolithic Integration Technologies for High Speed Front-end Photoreceivers

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題名:	高速前端光接收器之單石積體化技術;Monolithic Integration Technologies for High Speed Front-end Photoreceivers
作者:	黃維國;Wei-kuo Huang
貢獻者:	電機工程研究所
關鍵詞:	光電積體電路;磷化銦/砷化銦鎵;光二極體;異質接面雙載子電晶體;漸耦合光檢測器;單石積體化;全矽光接收器;Monolithically Integrated;InP/InGaAs;Photoreceiver;OEIC;p-i-n/HBT;ECPD/HBT;Photodiode;CMOS PD/TIA
日期:	2008-05-01
上傳時間:	2009-09-22 11:55:14 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	本論文提出了分別應用於1550 nm及850 nm波長高速前端光接收器的單石積體化技術。除了高速特性的需求以外，所提出的技術皆是相容或是可完全利用標準商業製程所實現。與非單石技術相比較，這些技術能夠提供較簡單的封裝，所以可得到高良率及低寄生效應等優點，亦能減少成本。磷化銦/砷化銦鎵（InP/InGaAs）材料系統特性十分適合應用於高速長波長光通訊系統。而異質接面雙載子電晶（Heterojunction Bipolar Transistor；簡稱HBT）更是能在同一磊晶結構中同時提供主動元件HBT及p-i-n光二極體（Photodiode；簡稱PD），而不需要其它複雜的磊晶成長與製程步驟。論文首先利用了傳統上照式的方法設計製作了一InP/InGaAs p-i-n PD與單級共基極轉阻放大器(Transimpedance Amplifier；簡稱TIA）整合的光電積體電路（Optoelectronic Integrated Circuit；簡稱OEIC）。其光電轉換頻寬由於受到p-i-n PD的速度特性限制，其光電轉換頻寬僅有15.5 GHz（共基極TIA轉阻頻寬為34 GHz）。為了要改善PD的速度特性，所以提出了一漸耦合光檢測器（Evanescently Coupled Photodiode；簡稱ECPD）/HBT的整合結構。透過此側面照光結構可以改善原傳統方法中PD與HBT特性的取捨問題，其製作之ECPD俱有0.3 A/W光響應度（波長為1.55 um）與29 GHz的光電轉換頻寬，而整合之OEIC的頻寬可達38 GHz（TIA轉阻增益 = 32 dB-ohm?）。除此之外，覆晶整合方式之ECPD/HBT OEIC亦一起提出；其中InP晶片包含了一ECPD、一InP/InGaAs HBT及覆晶接合點，而覆晶凸塊與其他被動元件則製作在半絕緣砷化鎵基板上。其覆晶整合OEIC之光電轉換頻寬亦可達35.5 GHz。除了長波長的應用以外，論文在短波長的部份則使用標準矽（Silicon；簡稱Si）互補式金屬-氧化層-半導體（Complementary Metal-Oxide-Semiconductor；簡稱CMOS）製程技術製作之高速850 nm PD及其整合OEIC，由於使用低成本的Si製程製做，所以其研究成果可應用於需要低成本的短距離光通訊系統。然而對於標準CMOS製程製作之單石光接收器來說，雖然目前Si CMOS電路部份發展已相當成熟，但是在PD的部份，照光後來自深層基板所產生的慢速擴散載子卻大大影響了光響應速度，而這樣的問題已經嚴重地限制了OEIC的整合特性。所以，在論文中討論了CMOS PD速度特性的改善方法及其整合高速OEIC。首先提出了一利用臺灣積體電路製造股份有限公司（Taiwan Semiconductor Manufacturing Company Limited）標準0.18 um製程技術所製作之850 nm高速、高響應度雪崩光二極體（Avalanche Photodiode；簡稱APD），此APD俱0.3 A/W光響應度、1.6 GHz光電轉換頻寬。另外更利用基板電流來消除慢速載子的方法，當基板偏壓為10 V時可將APD的光電轉換頻寬再延伸至2.8 GHz。最後，設計一TIA與PD做整合，來證明高速全矽光接收器的可行性；當基板偏壓為8 V時，所設計之OEIC頻寬更可高達4.2 GHz。在未來工作部份，有針對ECPD結構切割容忍度、CMOS APD的功率消耗、多通道Si光接收器時的干擾及在CMOS後段製程中利用鍺材料來應用於高速、長波長吸收的PD在論文最後分別做討論。 This dissertation proposes several technologies for high speed monolithic front-end photoreceivers at 1550 nm and 850 nm wavelengths, respectively. Except for the requirement of the necessary high speed performance, the main idea of the proposed monolithic solutions are compatible or can be fully fabricated in standard commercial technologies without process modifications. Comparing to the hybrid approaches, the supplied advantage of the simpler package promises high yield and low parasitic effect, and thus reduces the cost. Monolithically integrated front-end photoreciever based on InP/InGaAs material system is very attractive because of the potential for high-speed operation in long-wavelength optical communication systems. Using same layer structure for photodiode (PD) and trans-impedance amplifier (TIA) provides the advantages of one-step epitaxy and simple fabrication. An example of the shared layer integration scheme in this design is the p-i-n PD/HBT photoreceiver in which the p-i-n PD is made with the base-collector layers of the HBT structure without any complex growth and fabrication sequence. In this dissertation, a conventional top-illuminated InP/InGaAs p-i-n PD/HBT structure and the integration of a PD with a single stage common base TIA are designed, fabricated and characterized. A -3 dB electrical bandwidth of 15.5 GHz is obtained for the integrated circuit though a higher bandwidth of 34 GHz is observed for the TIA only. The bandwidth of this optoelectronic integrated circuit (OEIC) is mainly limited by the characteristic of the p-i-n PD. In order to improve the response time of the PD and the inherent trade-off problem in the conventional type, the novel structure of the combined InP evanescently coupled photodiode (ECPD)/HBT is proposed and applied in the monolithically and flip-chip assembled OEICs. The ECPD/HBT approach overcomes the limitations of the PD and the trade-off problem in the conventional solution. The fabricated ECPD with a thinner absorption layer exhibits a higher responsivity of 0.3 A/W and a -3 dB electrical bandwidth of 29 GHz. The integrated ECPD/HBT receiver demonstrates a -3 dB electrical bandwidth of 38 GHz with a transimpedance gain of 32 dB-ohm. In the flip-chip assembled OEIC, it comprises an InP chip and the carrier substrate. The InP chip consists of an ECPD, an InP/InGaAs HBT and the bonding pads. The semi-insulating GaAs carrier consists of all other passive components. The OEIC demonstrates a -3 dB electrical bandwidth of 35.5 GHz with a transimpedance gain of 32 dB-ohm. Except for the long wavelength (1550 nm) application, the short wavelength (850 nm) application is also discussed to enable cost-effective implementation of optical short-distance interconnect in standard Si CMOS technology. Since Si CMOS technology provides an universal platform for monolithic integration of complex circuits and can be monolithically integrated with Si PD (850 nm) to form an all-Si optical receiver. However, the diffusion photocarriers which are generated from deep substrate diffuse slowly to the depletion region in the Si PD and result in a slow photo-response. This imposes severe limitations on the receiver architecture and performance. Hence the Si PD which is a crucial issue in CMOS OEIC is investigated and proposed. A new high-speed and high-responsivity avalanche photodiode (APD) with multiple p+-p-n diodes structure by standard TSMC 0.18 um CMOS technology is presented without any process modifications. The designed PD demonstrates a high responsivity of 0.3 A/W, a -3 dB bandwidth of 1.6 GHz, and an eye diagram at 3.5 Gb/s. Another novel method is also proposed to eliminate the slow photocarriers by using body contact design to create a current path under the PD. The novel PD with body contact (VB) of 5 V and 10 V shows higher modulation ratio than PD with floating VB. The measured eye diagram at data rate of 2.5, 4, and 5 Gb/s are also demonstrated. Finally, the monolithically integrated OEIC in standard 0.18 um CMOS technology which is based on the experience of the previous designed PDs is designed to verify the feasibility of the high speed all-Si photoreceiver. The OEIC demonstrates the -3 dB bandwidth of 4.2 GHz with VBP of 8 V. With the cable connected amplifier, the receiver shows clear eye diagram at 2.5 Gb/s and meets the mask of SONET OC-48. In the future work, the improvement of the cleaved tolerance in ECPD structure, the power dissipation in the proposed CMOS PD with body contact, the crosstalk of multi-channels application in CMOS technology, the Ge material in CMOS back-end process are proposed to further improve the current PDs and OECIs.
顯示於類別:	[電機工程研究所] 博碩士論文

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