摘 要 在驗證的過程當中，除錯通常是一件困難且費時的工作，而且這項艱鉅的工作現在仍然需要設計者本身自己親自去做。在整體設計的流程當中，因為錯誤的發生通常都是在設計最初的時段，因此有許多針對於設計者在撰寫HDL階段時的除錯方式被提出來。在[7]這篇論文當中，作者提出了一個將所有可能發生錯誤的部份依照其可能發生錯誤機率的大小依序排列出來，因此設計者只需要根據所列出的這些可能發生錯誤者加以追查就能找到設計上錯誤的地方，因此可以大幅的減少設計者在除錯上面所需要花費的時間或是人力。然而這樣的方式卻缺乏內部的資訊所以對於每個預估錯誤部份機率的可能性仍然不是非常準確。在我們這篇論文中，我們提出一種新的方式，利用assertions來增加額外的可見性，因此對於錯誤機率更能夠準確的估測。使用我們的方法所建立起來的錯誤序列將比先前論文所做的更加準確，因此設計者在除錯上所需花費的人力更能夠減少。在以下的實驗數據中可以看出我們有效的改善成果。 Abstract In the verification process, debugging is also a hard and time-consuming process and is often done by designers themselves. Because most design errors occur in the early design stages, there are also some approaches proposed for debugging HDL designs. The authors in [7] proposed a method to give a rank to each error candidate such that the efforts of debugging can be reduced because designers only have to trace several items in the front of list. However, due to lack of internal information of the circuit, the estimation of error possibility may still not very accurate. In this paper, we propose a method to use the extra observability provided by assertions to make a better estimation of error possibility. Using our approach, the error ranking can be more accurate than that in previous approach such that the debugging efforts can be further reduced. The effectiveness of our improvements can be shown in the experiments.
