論文最前面的部份，提出一個疊接形式的雙閘極金氧半場效電晶體模型。此大訊號模型包含了兩個傳統的BSIM3v3做為內部非線性模型，而外部被動網路則是由具有物理意義為基礎的寄生元件所組成。這些位於閘極、源極以及汲極上，所寄生的電阻、電感則是利用量測到的S參數計算萃取出來。所建立的雙閘極元件模型在小訊號S參數以及功率特性上，模擬與量測結果頻率從50 MHz ~ 15 GHz則是相當的吻合。最後並設計了雙閘極2.4 GHz的低雜訊放大器以及混波器用以驗證所提出模型的準確性。此外，論文裡提出了一個新穎的三次轉導相消的方法，並且設計於一個2.4 GHz的射頻混波器上改善電路的線性度。由於基極到源極的偏壓大小可以改變三次轉導鋒值的位置，將兩顆具有正負三次轉導鋒值的電晶體，以並聯的方式連接這樣即可以達到三次轉導相消的結果。元件的量測結果顯示，鄰近頻道功率比以及輸入三次調變失真點都改善了15 dB。在混波器的設計方面，由於轉導級是貢獻混波器非線性特徵的來源，將具有三次轉導補償的元件取代混波器的轉導級做設計即可達到線性度的改善。最後量測結果顯示，鄰近頻道功率比以及輸入三次調變失真點分別改善了10 dB以及15 dB。 論文另一個部份，提出了一個具有6 GHz寬頻低電壓以及低功率操作的降頻混波器架構。並且以標準的0.18微米金氧半場效電晶體製程實現。這個新穎的混波器是利用疊接的架構以及基極端注入的技術，達成低電壓以及低功率的電路特性。此混波器當工作頻率在2.4 GHz時，具有6 dB的電路增益以及單端頻帶雜訊指數15.2 dB，而線性度方面輸入三次調變失真點為0 dBm。此外，電路核心所需的面積只要0.15 × 0.23 mm2。當中頻頻率固定為100 MHz時，量測到的射頻3-dB頻寬可以從0.5 GHz到6 GHz。在最佳的工作電壓0.7 V操作下，電路只需要0.4 mA的電流損耗。如此低電壓以及低功率操作特性，可以與高階製程技術90或是60奈米製程等相互比較。 論文最後一個部份，設計了一個具有高品質係數的主動式電感。在一般常用的疊接式架構上增加了一個回授電阻以及調整增益的電晶體，如此一來主動式電感的品質係數將可以改善增加。此新穎的主動式電感操作在4.3 GHz時具有3.2 nH的電感值以及最大540的品質係數。最後並利用主動式電感設計了一個主動式的帶通濾波器，此濾波器具有很低的傳輸衰減值0.2 dB反射損耗32 dB，並且濾波器中心頻率經由電壓的改變可以從3.45 GHz調整到3.6 GHz。 This thesis covers the design of low-power high-linearity CMOS mixers. In the first part of this dissertation, a cascode dual-gate CMOS model is presented. The proposed large-signal model consists of two intrinsic conventional BSIM3v3 nonlinear models and the passive network represents the physical-based parasitic components of the device. The extrinsic elements of substrate networks, and the distributed resistances and inductances of gate, source and drain terminals are calculated from the measured S-parameters. Good agreement form 50 MHz to 15 GHz has been obtained between simulation and measurement of small-signal S-parameters and power characteristics. In order to verify the model accuracy, a 2.4 GHz dual-gate LNA and mixer were designed and tested. Moreover, a new third-order transconductance (gm3) cancellation technique is proposed and applied to a 2.4 GHz conventional RF mixer for improving circuit linearity. The bulk-to-source voltage is applied to adjust the peak value position of gm3. The cancellation of gm3 is utilized by a negative peak gm3 transistor combining in parallel with a positive peak gm3 transistor. For a single device, the measured adjacent channel power ratio (ACPR) and third-order intermodulation (IMD3) distortion are both improved over 15 dB. The compensated gm3 device is placed in the input RF gm-stage, thus reducing the principle nonlinearity source of the mixer. From the experiment results, the ACPR and IMD3 of the mixer are improved about 10 dB and 15 dB, respectively. An ultra broadband low-voltage low-power down-conversion mixer using a 0.18-µm standard CMOS process is also presented. The proposed mixer uses a novel cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at radio frequency (RF) of 2.4 GHz, a single-side band (SSB) noise figure of 15.2 dB, and an input IP3 of 0 dBm. Moreover, the chip area of the mixer core is only 0.15 × 0.23 mm2. The measured 3-dB RF frequency bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum dc supply voltage (VDD) can be scaled down to 0.7 V with a 0.4 mA drain current. The supply voltage and dc power of this circuit can be compatible with an advanced 90-nm or 60-nm CMOS technology. In the last part of this dissertation, a high quality-factor active inductor has been demonstrated. By adding a feedback resistance and a regulated gain stage transistor into the conventional cascade-grounded approach, the quality-factor and performance of CMOS active inductor can be improved. This novel active inductor demonstrated a maximum quality-factor of 540 and a 3.2 nH inductance at 4.3 GHz, where the self-resonant frequency was 5.4 GHz. An active CMOS band-pass filter was also fabricated including this tunable high quality factor active inductor, giving an insertion loss of 0.2 dB and a return loss more than 32 dB with a tuning range from 3.45 GHz to 3.6 GHz.
