自我修復記憶體之備份分析評估與驗證平台; An Evaluation and Verification Platform for Built-In Redundancy Analysis Schemes of Self-Repairable Memories

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9838

Title:	自我修復記憶體之備份分析評估與驗證平台;An Evaluation and Verification Platform for Built-In Redundancy Analysis Schemes of Self-Repairable Memories
Authors:	張達銘;Da-Ming Chang
Contributors:	電機工程研究所
Keywords:	evaluation;verification;platform;BIRA;BISR;built-in redundancy analysis scheme
Date:	2005-07-06
Issue Date:	2009-09-22 11:57:30 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	嵌入式記憶體是現今系統晶片中最常被使用到核心。根據2001年International Technology Roadmap for semiconductor (ITRS)，現今系統晶片中，超過50%晶片面積會被嵌入式記憶體所佔據。所以當嵌入式記憶體有缺陷(defect)發生時，會大幅的降低整體系統晶片的製造良率。所以對於系統晶片良率的提升，可修復的嵌入式記憶體扮演一個重要腳色。為了降低實現可修復的嵌入式記憶體所必須付出的代價，可以利用內建式自我測試與內建式備份分析去實現低成本的可修復的嵌入式復記憶體。由於嵌入式記憶體中的備份元件的使用效率取決於備份分析的演算法，所以如何快速地找到一個有效並且經濟的備份分析的演算法是重要的。在這篇論文中，提出一個平台可以幫助使用者評估所提出的內建式備份分析演算法的好壞並且進一步去驗證所設計的電路功能是否符合所推導的備份分析的演算法。在平台中可以依據使用者所訂的記憶體一些參數與備份元件的種類與數量去評估出備份分析的演算法在這樣的狀態下的修復率。進一步可以分析壞掉的記憶體在測試機台所產生的錯誤資訊(fail log file)在這樣的備份分析的演算法錯誤的記憶體是否可以修復。針對驗證備份分析演算法的實現電路方面，這個平台能夠產生測試樣本(test pattern)去驗證它的功能是否與所推導的備分分析的演算法相同並且正確。除此之外我們針對可修復的記憶體擁有備份行、備份列與備份字元提出一個備份分析的演算法，利用所建立的平台去做分析，這個演算法在記憶體大小為，並且擁有一個備份列(一個備份列可視為128個備份字元組)、兩個備份行與兩個備份字元作修復率分析時，其修復率可相同於最佳的備份分析的演算法(Exhaustive Algorithm)在相同的記憶體大小、錯誤分佈與錯誤狀態但其擁有三個備份列與兩個備份行。針對的記憶體且擁有三個備份列、三個備份行與兩個備份字元，利用此演算法將完整的BIRA電路實現出來只增加了2.01%的記憶體面積。 Embedded memory is one of the most widely used cores in system-on-chips (SoCs). According to the 2001 International Technology Roadmap for Semiconductor (ITRS), the embedded memories currently occupy more than 50% of the system on chips (SoCs). The defects in the embedded memory arrays can significantly degrade manufacturing yield. So the repairable embedded memories play an important role for the improvement of SoC yield. To reduce the cost of the repairable embedded memory implementation, the repairable embedded memories are implemented by built-in self-test (BIST) and built-in redundancy-analysis (BIRA). The efficiency of the redundancy depends on the RA algorithm. Thus it is important to find an efficient and economical RA algorithm rapidly. In this thesis, we present a platform for the evaluation and verification of BIRAs. It can calculate the repair rate with respect to the specification of the memory and the spare element or the information from the fail log file. The platform can generate the test benches for the BIRA functional verification. We also propose an efficient RA algorithm for a memory with spare rows, spare columns, and spare words. Simulation results show that the repair rate of the proposed RA algorithm for an -bit memory with one spare row (one spare row = 128 spare words), two spare columns, and two spare words is the same as the repair rate of the exhaustive RA algorithm for the same memory with three spare rows and two spare columns. The area cost of the proposed BIRA architecture is only 2.01% of an -bit memory with three spare rows, three spare columns and two spare words.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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