隨著製程技術的進步，元件尺寸越來越小。在這樣的單晶片設計(SoC)的潮流之下，面對整合數百萬個邏輯閘個數在單一晶片裡，傳統的電路設計技巧不再適用，必須改變設計方法來解決電路整合的問題。單晶片的時代裡，混合訊號(mixed-signal)系統設計的挑戰主要可以分成一起模擬(co-simulation)以及雜訊交互影響(noise interaction)兩個問題。對於現代的大電路設計來說，整合在佈局階層以及低階層的佈局後(post-layout)一起模擬(co-simulation)變的幾乎不可行。此外，隨著電源電壓的越來越小，以及電路的操作速度越來越快，電源的變動將會主宰整個系統的效能，因此這種效應不應該再被忽略。 在這篇論文裡面，我們以鎖相迴路(phase-locked loop)為例子，提出了考慮電源雜訊(supply noise aware)的類比電路行為模型(behavioral model)，期望可以用這樣的行為模型來評估、解決上述的兩個整合的問題。在我們的方法中，我們提出了一個由下往上(bottom-up)的萃取流程(extraction flow)，用很 短的時間來獲得鎖相迴路行為模型所需的電路特徵參數。然後，我們修正這些參數，使的即使在不同電源電壓的情況下，我們的方法只需要跑三次佈局後的模 擬，就能建立精準地反應電源雜訊的行為模型。 在實驗結果裡面，我們可以很明顯的看出，對於電源雜訊的效應來說，我們的方法不需要耗時的相關分析，就能有很精準的輸出響應(responses)。 With the process technology innovating rapidly, the device size is continuing to scaling down. In the trend of SoC designs, traditional design techniques must be modified to solve the integration problems with over million gate counts in a single chip. In SoC era, the major design challenges are the issues of co-simulation speed and noise interactions in a mixed-signal system. Integration at layout level and running the low level post-layout simulation become almost infeasible for the modern large designs. Moreover, the supply voltage fluctuations cannot be ignored any more and these effects will dominate the system performances with faster switching frequency and smaller supply voltage. In this thesis, we propose the supply noise aware behavioral models for analog circuits, such phase-locked loop circuits, in order to estimate and handle these two integration issues. We present a bottom-up extraction flow to extract the characteristic parameters for PLL behavioral models in a short time. Then, we adjust these parameters for considering the supply noise effects such that only three post-layout simulations are enough to generate accurate behavioral models under various supply voltages. The experimental results have shown that this approach can really have accurate output responses under different supply voltages without time-consuming correlation analysis.
