| 摘要: | 近年來,接收系統中的數位電路及基頻電路部份已進入SoC時代，而CMOS具有低成本及高整合度兩大特性，提高了射頻前端電路邁向SoC的可能性，因此CMOS製程在射頻前端電路應用上的需求便大量的提昇。功率放大器在射頻前端電路中佔有相當重要的地位，在一個無線系統中，高效率的功率放大器是很吸引人的，因為射頻前端電路最主要的功率消耗來源就是功率放大器。近年來在無線通訊市場上的可攜式產品，除了收發良好的基本功能外，產品的待機時間已是重要的考量之一，因此在射頻收發機中最佔耗電量的功率放大器其功率增加效率要越高越好以降低熱損耗，減少能量消耗並因此提高電晶體的可靠度。 目前我國數位電視仍未全面普及,在未來幾年,數位電視將會漸漸取代現今的類比電視。射頻接收機處理天線接收後的訊號,也就是說射頻接收機是處理數位電視訊號的第一道關卡。要建立全面的數位電視時代,除了發送信號平台的建立,接收設備也是相當重要的一環,因此數位電視訊號接收端的電路便顯得格外重要。 本論文主要研究內容為應用在無線區域網路的射頻功率放大器設計，以及應用在數位地面電視射頻前端的低雜訊放大器設計。論文中電路皆以台積電0.18微米互補式金氧半導體製程。 功率放大器部份，2.4GHz A類功率放大器功率增益為8.8dB、輸出1-dB壓縮點為19.8dBm、功率增加效率為12.8%而輸入三階截斷點為25dBm 。2.4GHz 可調輸出功率之功率放大器量測結果發現頻率漂移至1.2GHz ，在1.2GHz量測結果為:高輸出功率模式下，功率增益為7.4dB、輸出1-dB壓縮點為19.5dBm、功率增加效率為17.9%而輸入三階截斷點為21dBm; 低輸出功率模式下，功率增益為7.3dB、輸出1-dB壓縮點為12.3dBm、功率增加效率為4.3%而輸入三階截斷點為22dBm。利用二極體偏壓電路的2.4GHz高功率增加效率功率放大器之頻率漂移至2.7GHz,在2.7GHz的功率增益為10.6dB、輸出1-dB壓縮點為19.6dBm、功率增加效率為17.5%而輸入三階截斷點為23dBm。 寬頻低雜訊放大器在操作頻帶內增益大於7.4dB、雜訊指數低於4.3dB、輸入三階截斷點大於11dBm而輸入二階截斷點大於34dBm。 In recent years, digital circuits and baseband circuits in the receiver have entered the age of SoC (System-on-a-Chip). Owing to the characteristics of low cost and high integration, submicron CMOS technology provides a probability of SoC implementation for RF front-end. Thus, the submicron CMOS processes are of great demand for RF front-end. Power amplifiers are the important component in the RF Front-End. In a wireless system, a high efficiency power amplifier is attractive because it is the main source of power dissipation in the RF front-end. In these years, not only the capability to receive and transmit signals, but also time for stand by of the portable products in wireless communication have been taken into seriously account. To decrease the loss of heat, the power added efficiency (PAE) is the higher, the better. As the loss of energy decreases, the reliability of the transistors rises. The Digital Terrestrial TV is not popular so far. However, digital TV will gradually replace analog TV in the coming years. The RF receiver deals with the signal received by antenna, that is, the RF receiver firstly handles the signal of digital TV. Besides the stations for transmission, the equipments for receiving signal are also important. Thus the circuits of digital TV receiver are quite significant. The main researches in this thesis are the RF power amplifiers for WLAN applications and a wide-band low noise amplifier for DVB-T RF front-end receiver. The circuits in this thesis are implemented in tsmc 0.18um CMOS process. In the section of PAs, measured linear gain of the 2.4GHz class A power amplifier is 8.8dB with output 1-dB compression point (P1dB) of 19.8dBm, and the measured power added efficiency (PAE) at P1dB is 12.8% with the input third interception point (IIP3) of 25dBm. The power amplifier with switched output power is originally designed for 2.4GHz applications but the operation frequency is turned into 1.2GHz after measurement. The measured linear gain is 7.4dB with output P1dB of 19.5dBm, and the measured PAE at P1dB is 17.9% with IIP3 of 21dBm for high output power mode; For low output power mode, linear gain is 7.3dB with output P1dB of 12.3dBm and PAE at P1dB is 4.3% with IIP3 of 22dBm. The measured results of high PAE power amplifier with a diode bias circuit are as follows: Operation frequency of 2.7GHz with power gain of 10.6dB. The output P1dB is 19.6dBm, and the measured PAE at P1dB is 17.5% with IIP3 of 23dBm. The wide-band low noise amplifier achieves at least gain of 7.4dB with noise figure lower than 4.3dB, and IIP3 is higher than 11dBm with the second input interception point (IIP2) higher than 34dBm. |
