此篇論文描述了數個射頻電路的設計，並運用於寬頻化碼多工進接系統中，採用台積電0.35微米矽鍺雙載子互補金屬氧化半導體製程。以下依各章節不同的電路來分類，概述論文中各電路的實際量測結果。 第三章為升頻混頻器的設計，包括了兩種混頻器，一種是摺疊電流式的升頻混頻器，另一種是雙端平衡式的基級升頻混頻器。第一個混頻器約有0.9dB的轉換增益、輸出1-dB增益壓縮點為-9dBm、輸出三階截斷點在3dBm、射頻埠和中頻埠和本地振盪源埠之間的隔離度均大於40 dB。第二個混頻器約有3.9 dB的轉換損耗、輸出1-dB增益壓縮點為-14dBm、輸出三階截斷點在0 dBm、射頻埠和中頻埠和本地振盪源埠之間的隔離度均大於35 dB。 第四章為壓控振盪器的設計，設計中心頻率為1.94GHz，包括了兩個壓控振盪器，一個是切換式電容陣列的壓控振盪器，另一個是具有似固定的控制增益(quasi-constant KVCO)的壓控振盪器。第一個壓控振盪器具有351 MHz的振盪頻率調整範圍、約-9 dBm的輸出功率強度、在與振盪頻率距100 kHz頻偏的量測條件下約-93 dBc/Hz的相位雜訊。第二個壓控振盪器具有137 MHz的振盪頻率調整範圍、41 MHz/V 的控制增益、約-7 dBm的輸出功率強度、在與振盪頻率距100 kHz頻偏的量測條件下約-93 dBc/Hz的相位雜訊。 This thesis describes several radio frequency circuit designs, which are adopted in W-CDMA application. They are implemented with tsmc 0.35mm SiGe BiCMOS process. The following sections will summarize the practical measured results classified by different circuits in different chapters. Chapter 3 introduces the designs of up-conversion mixers, including current-folded up-conversion mixer, and double-balanced base up-conversion mixer. These circuits are measured on FR4 print circuit boards. The former has conversion gain of 0.9dB, output P1dB of -9dBm, output IP3 of 3dBm, and isolation between each two ports, which is superior to 40dB. The latter has conversion loss of 3.9dB, output P1dB of –14dBm, output IP3 of 0dBm, and isolation among all ports are superior to 30dB. Chapter 4 presents the designs of VCOs whose center frequencies are 1.94GHz, including a switched capacitance array VCO, and a quasi-constant KVCO VCO. These circuits are measured on FR4 print circuit boards. The former obtains a tuning range of 351MHz, and output power of -9dBm, and phase noise of –93.7dBc/Hz at 100KHz offset. The latter yields a tuning range of 137MHz, average KVCO of 41MHz/V, and output power of -7dBm, and phase noise of -93dBc/Hz at 100KHz offset.
