超寬頻系統多頻帶發射機及寬頻主動90°相位差電路設計; Design of UWB Multi-Band Transmitter and Broad-Band Active 90° Phase-Difference Circuits

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9858

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9858

Title:	超寬頻系統多頻帶發射機及寬頻主動90°相位差電路設計;Design of UWB Multi-Band Transmitter and Broad-Band Active 90° Phase-Difference Circuits
Authors:	賴奇郁;Chi-Yu Lai
Contributors:	電機工程研究所
Keywords:	phase shifter;mixer;vco;CMOS;UWB
Date:	2006-01-06
Issue Date:	2009-09-22 11:58:05 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	由於無線通訊及傳輸的便利，無線系統的應用已經普遍且深入我們的生活領域。隨著越來越多的無線傳輸應用，現今對大量資料傳輸系統的需求已經變的更加迫切，因此，我們需要更高的資料傳輸速率系統規範。超寬頻系統就是一個很顯著的高資料傳輸速率系統規範，具備3.1 GHz到10.6 GHz，共計7.5 GHz的頻寬系統應用規範。而跳頻式多頻帶正交分頻多工技術 (BH-MB-OFDM) 是被使用於應用在高資料傳輸速率存取的用途。本論文主要研究內容為應用在超寬頻模組Group-A頻段發射端LO產生器之壓控振盪器和混頻器設計，以及應用在單頻帶混頻器的寬頻主動90°相位差電路設計。論文中電路皆以台積電0.18微米互補式金氧半導體製程。壓控振盪器的設計中心頻率為3.96 GHz，量測結果漂移到3.83 GHz，壓控振盪器具有330 MHz振盪頻率調整範圍和 -24.7 dBm的輸出功率強度，在與振盪頻率距100 kHz頻偏的量測結果約為 -89.1 dBc/Hz相位雜訊。內建式濾波可切換雙頻混頻器，其模擬結果輸出電壓擺幅為0.1 V及旁波帶抑制比達到良好的30 dBc，晶片面積包含接觸墊只有0.68×0.78 mm2且功率消耗為17.6 mW。寬頻主動90°相位差電路設計，操作頻率為2到6 GHz。量測結果漂移成為1到3 GHz，在相同頻率下，兩輸出端的相位差不平衡小於10°，兩輸出端的振幅不平衡小於 ± 2.5 dB。 Due to the convenience of wireless communication, the wireless applications are popular and go deep into our life. As more and more applications trend to wireless, the data rate of the systems nowadays become not allowable. Thus, new high-data-rate standards are required. One of the conspicuous, high-data-rate standard is the Ultra-Wideband (UWB) with a total bandwidth of 7.5 GHz from 3.1 GHz to 10.6 GHz. The Band Hopping Multi-Band Orthogonal Frequency Division Multiplexing (BH-MB-OFDM) technique is used for multiple accesses purpose. The main researches in this thesis are the voltage-controlled-oscillator and mixer of LO generator for UWB multi-band group-A transmitter and the broad-band active 90° phase-difference circuit for single-sideband mixer. The circuits in this thesis are implemented in tsmc 0.18μm CMOS process. The measured center frequency of VCO is 3.83 GHz with tuning range 330 MHz and the output power is -24.7 dBm. The phase noise is -89.1 dBc @ 100 kHz offset. The simulated results of the mixer show 0.1 V output voltage swing and good 30 dBc side-band compression. The chip area of mixer is 0.68×0.78 mm2. The power consumption of this circuit inclued buffer stage is 17.6 mW. The measured result of phase shifter shows the operation frequency range from 1 to 3 GHz, and the phase unbalance between the output terminals across the bandwidth is less than 10° error, and the ± 2.5 dB of amplitude unbalance is achieved.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Size	Format

社群 sharing

Loading...