在本篇論文中，將介紹除法器完整的設計和實現。主要是為了設計出一個高速基底4的除法器，利用數值重複循環的方式。一般傳統SRT除法器的商值是用PLA or ROM 實現，不僅花費時間長且面積龐大。本論文的演算法是利用拉大商值來擴大可選取的區域，來簡化選擇商值的電路設計。將商值分成二個部份去做運算，同時做二個不同商值的運算得到二個不同的餘數，再依據餘數做一次商值的選擇，得到正確的商數跟餘數。用此方法在商值的電路設計上會簡化許多而且會加快整體速度。此外 ，使用簡單的邏輯電路來實現商值電路且改善它的整體速度。最後，我們使用 0.18μm CMOS 製程來實現雙精準度除法，它整體運算時間為50.8ns。 The design of a fast divider is an important issue in high-speed computing. This study presents fast radix-4 SRT division architecture with the digit-recurrent approach. Digit-recurrent division is an algorithm in which the quotient is obtained one digit per iteration. In this study, instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, this two-step process does not influence the overall speed. Since the decision making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit achieves 50.8ns for a double precision division (56 bits for fraction part), where the TSMC 0.18μm CMOS technology is employed and simulated.
