2.5Gbps串列收發器設計; Design of CMOS Transmitter Circuit for 2.5Gbps NRZ Data Transmission

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/9866

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题名:	2.5Gbps串列收發器設計;Design of CMOS Transmitter Circuit for 2.5Gbps NRZ Data Transmission
作者:	郭世雄;shin-Syong Guo
贡献者:	電機工程研究所
关键词:	串列器;發射器;serial;tramsmitter
日期:	2005-07-08
上传时间:	2009-09-22 11:58:19 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	摘要最近幾年網路以及電腦運算速度的演進的帶動下，興起一股朝向資料傳輸和高速串列資料通訊研究的潮流。由PCI 1.0演進至目前的PCI-Express，正說明了在高資料量傳輸時傳統平行介面技術逐漸由串列介面技術所取代。然而串列傳輸技術過去主要用於光纖通訊並用來取代PC板上高速匯流排。串列傳輸技術由一種分時多工、點對點的通訊技術，即在發送端將低速的平行訊號轉換為高速的串列信號。在接收端再將高速列列信號重新轉換為低速的平行訊號。本論文著重在有線(wire)或匯流排的串列資料傳輸的應用(例如USB2.0、IEEE1394b、SERIAL-ATA、PCI-EXPRESS)，並以PCI-Epress之規格做為實現之目標。本論文利用多重相位鎖相鎖路之時脈特性對串列器做出時間上的區分，達到分時多工的目地將平行資料轉換成串列訊號。在輸出終端方面，由於傳輸線的效應在高速訊號的完整性有著重大的影響。故本論文利用精準的比較電壓控制調整負載的阻抗，使輸出驅動器具有50歐姆阻抗使之與50歐姆傳輸線匹配。本論文以TSMC 0.18μm 1P6M CMOS製程來實現，工作電壓為1.8V。其串列發射器可操作在2.5Gps，其輸料資料眼圖抖動符合PCI-Express 1.0a所規範。測試晶片操作於2.5Gps資料率時，功率消耗為91.24mW，晶片面積(包含PAD)為685μm×685μm。 Design of CMOS Transmitter Circuit for 2.5Gps NRZ Data Transmission Abstract Under the development of the network and computer operated speed in recent years, a trend of data transmission and studying at high-speed serial communication is growing. It is pointed out that the high-speed serial link interface is replacing gradually the conventional parallel bus interface in large data transmission by the development of PCI bus from PCI 1.0 to PCI-Express. The serial link technique is used at the optical communication in the past. However, it replaces the high-speed parallel data bus. The serial link technique is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. This thesis focuses on the application of wire communication or serial link data transmission interface and takes the specification of PCI-Express as the objective in implementation. This work uses the multi-phase clock to generate the serial signal. In the output driver end, there is a large influence on the signal integrity due to the transmission line effect. So, this work achieves the well impedance match by adjusting the load. This thesis implements the transmitter chip fabricated in a TSMC 0.18μm CMOS technology. The transmitter operates at 2.5Gbps with 1.8V supply and the chip area is 685μm×685μm. The whole chip power consumption is 91.24mW.
显示于类别:	[電機工程研究所] 博碩士論文

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